AI is embarrassingly parallel and thus you can substitute a powerful AI chip with a large number of less powerful chips. But the main bottleneck for China is still the lack of EUV. Without EUV they will get further and further behind as US companies produce less than 1 nm chips while China is stuck at 7nm with very low yield 5nm production due to lack of EUV.
Chinese semiconductor thread II
- Thread starter vincent
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hmm, that's not how things work.
I would really hope that this forum understand by now that AI vs EUV is a pointless argument and that Western investment banks probably aren't fully up to date on Chinese chip consumption.
Not necessary, is bit complicated than that, EUV is not a replacement for chip architecture and packaging scaling. but they are getting there.
Also there will probably not be below 1nm process, double patterning with EUV is already insane expensive, QP would be prohibitive with EUV, my guess is that chip manufacturing would go 3D integrated.
Ironically the first "1nm" chip was a 32bit RISC processor on Sapphire from Fudan Univ. Didn't even required EUV, Just pure ALD and ALE.
With an investment of 3.5 billion yuan, Qingyi Optoelectronics' high-precision flat panel display photomask project is about to enter mass production.
Shenzhen Qingyi Optoelectronics Co., Ltd., a leading Chinese photomask manufacturer, has announced that its high-precision flat panel display photomask project is on the verge of entering mass production, following a production commencement ceremony held at its Foshan Nanhai production base on November 14, 2025. In parallel, the company is accelerating preparations for the mass production of its high-end semiconductor photomask project, marking a significant milestone in China's efforts to localize critical semiconductor and display technologies.
The company has invested a total of 3.5 billion yuan to establish a comprehensive production base dedicated to photomasks for flat panel displays (FPD) and semiconductors:
- Flat Panel Display Photomask Project (2 billion yuan):
- Focuses on producing 8.6-generation and below high-precision FPD photomasks.
- Targets key display technologies including a-Si (amorphous silicon), LTPS (low-temperature polycrystalline silicon), AMOLED (flexible organic light-emitting diode), LTPO (low-temperature polycrystalline oxide), and MicroLED.
- Addresses growing demand for high-definition, flexible, and foldable displays, especially in the context of the 5G and AI era.
- Fills a critical domestic gap in high-end photomask production, enabling domestic substitution and reducing reliance on foreign suppliers.
- High-End Semiconductor Photomask Project (1.5 billion yuan):
- To be built in three phases, targeting 180nm to 28nm semiconductor processes.
- Aims to develop and industrialize high-node semiconductor photomasks, traditionally dominated by overseas manufacturers.
- Expected to break international monopolies, enhance China's semiconductor supply chain security, and support the country's self-reliance in core technologies.
The production capacity will reach 600,000 pieces per year! Latest news on Dinglong's polishing hard pads!
Dinglong Co., Ltd., a leading manufacturer in the semiconductor materials industry, has announced significant progress and future expansion plans for its polishing hard pad production capacity. As of the end of Q1 2025, the monthly production capacity at its Wuhan headquarters has reached approximately 40,000 pieces, equivalent to about 500,000 units per year. The company expects this capacity to further increase to 50,000 pieces per month (600,000 annually) by the end of Q1 2026, reflecting its strong commitment to meeting growing market demand.
In addition to hard pads, Dinglong's Qianjiang industrial park currently has an annual production capacity of 200,000 CMP (Chemical Mechanical Polishing) polishing pads and matching buffer pads, catering to the fine polishing needs of downstream semiconductor customers. This facility is currently in a capacity ramp-up phase for soft polishing pads, with the company actively working to improve utilization rates through market expansion and customer acquisition.
A major highlight of Dinglong’s growth strategy is the ongoing development of the "Optoelectronic Semiconductor Materials R&D and Manufacturing Center" at its Wuhan headquarters. Once completed, this project will significantly enhance the company’s production and R&D capabilities. It will add an annual production capacity of:
- 400,000 large silicon wafer polishing pads
- 4,000 tons of prepolymer
- 200 tons of microsphere foam
- 30 tons of alumina abrasive
- 50 tons of cerium oxide abrasive
The total investment for this project is approximately RMB 288 million, with RMB 155 million sourced from raised funds. The construction period is expected to last three years, and the center will also establish comprehensive R&D, analytical testing, and application evaluation capabilities for optoelectronic semiconductor materials.
Ruiote Technology Secures Key Patent for Dual-Frequency Laser Interferometer Reflector Adjustment in Lithography Machines
In a significant development for China’s semiconductor equipment industry, Tianjin Ruiotai Technology Co., Ltd. has successfully obtained a new utility model patent for an adjustment structure of the reflector used in dual-frequency laser interferometers within lithography machines. This innovation promises to enhance the precision and efficiency of optical alignment in semiconductor manufacturing, a critical step in the production of advanced microchips.
The patent, titled "Adjustment Structure of Reflector for Dual-Frequency Laser Interferometer of Lithography Machine", was officially granted by the State Intellectual Property Office (SIPO) and published under the authorization announcement number CN223637887U. The patent application was filed in January 2025, marking Ruiotai’s growing involvement in high-tech industrial innovation.
The newly patented structure introduces a novel mechanical design that simplifies the adjustment of reflectors in dual-frequency laser interferometers—key components used to measure and control the precise positioning of wafers during the lithography process. The structure includes:
In a significant development for China’s semiconductor equipment industry, Tianjin Ruiotai Technology Co., Ltd. has successfully obtained a new utility model patent for an adjustment structure of the reflector used in dual-frequency laser interferometers within lithography machines. This innovation promises to enhance the precision and efficiency of optical alignment in semiconductor manufacturing, a critical step in the production of advanced microchips.
The patent, titled "Adjustment Structure of Reflector for Dual-Frequency Laser Interferometer of Lithography Machine", was officially granted by the State Intellectual Property Office (SIPO) and published under the authorization announcement number CN223637887U. The patent application was filed in January 2025, marking Ruiotai’s growing involvement in high-tech industrial innovation.
The newly patented structure introduces a novel mechanical design that simplifies the adjustment of reflectors in dual-frequency laser interferometers—key components used to measure and control the precise positioning of wafers during the lithography process. The structure includes:
- A mirror body encased in a frame for structural support.
- An adjustment component connected to the top of the frame, enabling fine-tuning of the mirror’s angle.
- A turntable at the base of the frame, allowing rotational movement.
- A protective cover that not only shields the mirror and frame but also plays an active role in the adjustment mechanism.
- An arc-shaped plate housed within a cavity in the protective cover, allowing for smooth and controlled angular adjustments.
- An annular groove on the base that accommodates the lower part of the protective cover, ensuring stability during rotation.
This design enables more convenient and accurate adjustments while also protecting the sensitive components from accidental contact or misalignment during operation. The large-sized protective cover further improves ergonomics, making manual adjustments easier for engineers and technicians.
Dual-frequency laser interferometers are widely used in these machines for their high-resolution displacement measurements. However, the complexity of adjusting the reflectors has long been a challenge for engineers. Ruiotai’s new patent addresses this issue by integrating protection and adjustability into a single, streamlined structure.
Tianjin Ruiotai Technology Co., Ltd. has been quietly expanding its technological footprint. Founded in 2015, with a registered capital of 3 million RMB, the company is based in Tianjin and has recently begun to pivot toward industrial and mechanical innovation.
Dual-frequency laser interferometers are widely used in these machines for their high-resolution displacement measurements. However, the complexity of adjusting the reflectors has long been a challenge for engineers. Ruiotai’s new patent addresses this issue by integrating protection and adjustability into a single, streamlined structure.
Tianjin Ruiotai Technology Co., Ltd. has been quietly expanding its technological footprint. Founded in 2015, with a registered capital of 3 million RMB, the company is based in Tianjin and has recently begun to pivot toward industrial and mechanical innovation.
The nm designations are marketing terms used to define higher transistor density and superior transistor technology, such as GAAfet. So, even if the actual transistors never physically reach 1nm, companies will introduce more and more generations of chip fabrication processes and call them below 1nm. Intel already calls its next-generation process 18A (Armstrong). TSMC is expected to call its next-generation process 1.4nm.
The problem for China is that no matter how many expensive workarounds they implement, such as extreme multi-patterning, they are constrained by the physics of using DUV light for lithography compared to the much smaller wavelength of EUV light. This is going to become more and more prohibitively expensive and will likely cause a slowdown in achieving higher transistor density.
Huawei's advanced chip stacking technology on Ascend chips can make them more powerful on paper, but it uses more power and thus also generates more heat, which requires higher heat dissipation technology. They might be able to tolerate this kind of workaround for data center purposes, but computing on edge systems such as phones and laptops will fall further and further behind compared to US-designed chips for those devices.
Overall, unless they acquire or develop EUV within the next 2-3 years, they will become truly stagnant in high-speed, low-power, high-efficiency computing. Slowly, these problems will also slow down GPU speeds, as NVIDIA chips will be far more efficient and cram more cores per chip than what Huawei can achieve.
Thus, EUV is the linchpin, in my opinion, of the whole chip race. If China cannot figure out EUV quickly, nothing else will be able to stop them from falling behind.
Yes, the advance heat sink tech & cooling is no issues. You just use more chips.
strange thing to say for someone who probably has never run Qwen models on edge, lol. And you are wrong obviously.
They will have EUV by then, but it's really not the end all, be all. the full supply chain matters. "The chip race" is a strange term since there are different type of advanced chips & a lot of them don't require EUV. Are you just referring to AI chips or phone chips? Because if we are just talking about the latest logic node, then they are going to be behind even if they have EUVs. But if you are talking about memory chips, they've already caught up. If you are talking about analog chips, they are still quite a bit behind. If you are talking about MCUs, they are catching up. If you are talking about power chips, they are actually ahead.
I am talking about long-term stagnation for China without EUV. Yes, EUV is currently needed only for the most advanced logic nodes and not for other kinds of controller chips. But ten years ago, 32 nm used to be the cutting edge for logic nodes, and now that same cutting edge is being used for controller chips. What I mean is, over time, even controller chips become more advanced and require die shrinks and higher transistor density. I believe that in ten years, even controller chips will need EUV as they slowly add more advanced capabilities and require much less power consumption. The overall trend of computing technology is miniaturization and higher transistor count.
This is true for memory chips and other forms of chips too. Even if China has caught up for now on these kinds of chips using DUV and multi-patterning, over time, China will also fall behind in memory and other kinds of chips, too, since the US and other countries will start to use EUV to achieve further shrinks in size and can cram more transistors or cram more capacitors in a smaller space.
The main point is, without EUV, China is stuck at the current point of miniaturization, while the US and other countries can continue to shrink the size of transistors and other elements of a chip.
We have had little update on the progress of China's EUV program so far. We see news about bits and pieces concerning some elements of an EUV machine making progress. But putting them all together and also making it production ready will be a challenge, and we have not seen anything that tells us how soon EUV will be making chips in Chinese fabs.
I know I just saying that the pitch parameters are going to get so tight after 1nm that would required QP with and that is prohibitively expensive with HighNA EUV. The reason why ASML jumped to High-NA from LowNA was to avoid adding more patterning steps. Companies would rather pay for a machine TWO times more expensive than doing more patterning steps with EUV. My guess in the next generation instead of doing multi-patterning the will rely of advance packaging and 3D integration to get more performance. A reason why ASML is jumping into packaging machines now.
Yes and no, immersion is dirt cheap compared to EUV, especially with High-NA EUV. You go with HighNA EUV because you want to avoid to do multi-patterning, less steps, easier fabrication but not necessary cheaper, that is cutting edge chips prices are rising. But there are other resolution enhancing techniques like DSA that could keep immersion relevant even for advanced nodes. But the same techniques could be use for Low-NA EUV.
Either way, EUV is almost inevitable in China and is closer than most stooges think, 2027 to 2030. So China will have domestic Immersion and EUV scanners along side multiple types of lithography machines. And even if goal is not to compete directly with ASML <at the beginning>. I do think they will try be cost effective enough that with resolution enhancing techniques could proper China way forward towards 2nm and beyond.