Chinese semiconductor thread II

[sunnymaxi]

Because if we are just talking about the latest logic node, then they are going to be behind even if they have EUVs. But if you are talking about memory chips, they've already caught up. If you are talking about analog chips, they are still quite a bit behind. If you are talking about MCUs, they are catching up. If you are talking about power chips, they are actually ahead.

sir there is heavy research going on for next generation transistor design like CFET and FlipFET by institute of IC/CAS. they also filled couple of patents.. i think they will try to leapfrog competitors in Logic node once EUV will be available using these latest transistor design.. so let see

 

[playmaker1478]

AI is embarrassingly parallel and thus you can substitute a powerful AI chip with a large number of less powerful chips. But the main bottleneck for China is still the lack of EUV. Without EUV they will get further and further behind as US companies produce less than 1 nm chips while China is stuck at 7nm with very low yield 5nm production due to lack of EUV.

I'm a bit more optimistic, believing China could produce a functional EUV machine before the end of 2030. However, I'm less certain about the photoresist. While EUV improves patterning resolution and can address certain yield issues, its higher power requirements-which help mitigate photon-shot noise-create new challenges for photoresist materials.

Scaling to smaller nodes has been difficult for some time, which is why the industry has shifted its focus toward innovations in interconnect technology, chip stacking, and advanced packaging. Even within a given node, there are differentiators like backside power delivery.

If China can successfully develop both an EUV machine and the necessary photoresist, while also keeping pace with research in these other areas (and upcoming standards), it would be in a very strong position. To be honest, my greater concern is the photoresist. Even if a solution like SSMB-EUV comes to fruition, its success would still be fundamentally limited by photoresist capabilities.

 

[tokenanalyst]

I will go beyond, I am 99% convinced China already have immersion machines patterning 300 wafers from 2020 and 90% convinced that EUV machines has being patterning 300mm wafers from 2023 at least. All the development it seems to be basically improvement from previous development. AND A LOT only makes sense if you already patterning wafers with EUV. A lot of commercial companies appearing like if there's ALREADY a commercial supply chain for mass production of EUV lithography. My guess is that at least for know most these EUV pilot lines IC are pretty basic chips that allow these machines to print wafers so they can be improved.

 

[sunnymaxi]

I will go beyond, I am 99% convinced China already have immersion machines patterning 300 wafers from 2020 and 90% convinced that EUV machines has being patterning 300mm wafers from 2023 at least. All the development it seems to be basically improvement from previous development. AND A LOT only makes sense if you already patterning wafers with EUV. A lot of commercial companies appearing like if there's ALREADY a commercial supply chain for mass production of EUV lithography. My guess is that at least for know most these EUV pilot lines IC are pretty basic chips that allow these machines to print wafers so they can be improved.

that's correct.

one by one all blacklisted/sanctioned companies filling IPO like Moore Thread and MetaX.. interesting part is MetaX draw more investors than MT.

Cambricon revenue in the third quarter, a year-on-year increase of 1332.52%.. next year they have big plans.

 

[sunnymaxi]

I'm a bit more optimistic, believing China could produce a functional EUV machine before the end of 2030. However, I'm less certain about the photoresist. While EUV improves patterning resolution and can address certain yield issues, its higher power requirements-which help mitigate photon-shot noise-create new challenges for photoresist materials.

Scaling to smaller nodes has been difficult for some time, which is why the industry has shifted its focus toward innovations in interconnect technology, chip stacking, and advanced packaging. Even within a given node, there are differentiators like backside power delivery.

If China can successfully develop both an EUV machine and the necessary photoresist, while also keeping pace with research in these other areas (and upcoming standards), it would be in a very strong position. To be honest, my greater concern is the photoresist. Even if a solution like SSMB-EUV comes to fruition, its success would still be fundamentally limited by photoresist capabilities.

zero issue regarding EUV photoresist.. they have EUV photoresist for testing and evaluation. filled bunch of patents as well. but yeah scale up production is a different game.
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just one example..

China's first EUV photoresist standard, "Extreme Ultraviolet (EUV) Photoresist Test Method," is being published as a proposed project standard starting October 23rd, with a deadline of November 22nd. The drafting organizations of the standard include Shanghai University, Zhangjiang National Laboratory, Shanghai Huali Integrated Circuit Manufacturing Co., Ltd., and Shanghai Microelectronics Equipment (Group) Co., Ltd.

 

[tokenanalyst]

Everything seems like a improvement of things of machines that are already working in an EUV Integrated Circuit Pilot Line. "Oh is contaminating too much". "Lets improve the throughput from 50WPH to 100 WPH".


How you do EUV metrology if you aren't constally patterning wafers an EUV Integrated Circuit Pilot Line?

 

[playmaker1478]

Overall, unless they acquire or develop EUV within the next 2-3 years, they will become truly stagnant in high-speed, low-power, high-efficiency computing. Slowly, these problems will also slow down GPU speeds, as NVIDIA chips will be far more efficient and cram more cores per chip than what Huawei can achieve.

Those problem existed since the EUV ban. A more pressing matter is total compute, and to that end, it's not that bad. Huawei's optical interconnect is actually world-class. I believe they are ahead of Nvidia, because they're a networking company. If Huawei can scale optical interconnect until EUV hit production ready, then slower chips will not be a concern as compute can scale via interconnect (physical area and power might be though lol).

 

[tphuang]

I am talking about long-term stagnation for China without EUV. Yes, EUV is currently needed only for the most advanced logic nodes and not for other kinds of controller chips. But ten years ago, 32 nm used to be the cutting edge for logic nodes, and now that same cutting edge is being used for controller chips. What I mean is, over time, even controller chips become more advanced and require die shrinks and higher transistor density. I believe that in ten years, even controller chips will need EUV as they slowly add more advanced capabilities and require much less power consumption. The overall trend of computing technology is miniaturization and higher transistor count.

This is true for memory chips and other forms of chips too. Even if China has caught up for now on these kinds of chips using DUV and multi-patterning, over time, China will also fall behind in memory and other kinds of chips, too, since the US and other countries will start to use EUV to achieve further shrinks in size and can cram more transistors or cram more capacitors in a smaller space.

The main point is, without EUV, China is stuck at the current point of miniaturization, while the US and other countries can continue to shrink the size of transistors and other elements of a chip.

We have had little update on the progress of China's EUV program so far. We see news about bits and pieces concerning some elements of an EUV machine making progress. But putting them all together and also making it production ready will be a challenge, and we have not seen anything that tells us how soon EUV will be making chips in Chinese fabs.

NAND already went 3D because they could not be shrunk further.
DRAM at most can get to D1c? before they also must go 3D. For memory chips, the requirements for further improvement lie in the non-lithography equipment.

You still haven't explained on why you need to continue shrinking a lot of this stuff. there is a reason a lot of the process stop at 22/28nm nodes. All the cutting edge analog chips don't even need to get to that point.

There is no export restrictions around just designing phone SoC and having them fabb'd at TSMC.

So, the only thing left is the AI chips for data center. And we already have a Huawei roadmap for the next 3 years that state their super clusters will get to 2 ZFLOPS in compute. What more do you need?

 

[tphuang]

sir there is heavy research going on for next generation transistor design like CFET and FlipFET by institute of IC/CAS. they also filled couple of patents.. i think they will try to leapfrog competitors in Logic node once EUV will be available using these latest transistor design.. so let see

let's do one step at a time. I'm not a fan of just reading research and putting a timeline on them.