I don't think this is Silergy. Silergy website is here
this is 思尔芯
Chinese semiconductor thread II
- Thread starter vincent
- Start date
I don't think this is Silergy. Silergy website is here
this is 思尔芯
The news is from their own website. Could be a mistranslation.
Their name is S2C EDA, the Silergy could come from the "S"
DRAM – Q3 2025 Update
1. Executive Summary
In this third issue of the 2025 DRAM quarterly update, TechInsights provides an update on the ongoing DRAM analysis. This issue also looks at the recent Winbond, Nanya, and CXMT devices and recaps the 10 nm class DRAM nodes.
2. Recent devices from Winbond, Nanya, and CXMT
Table 2.0.1 shows the recent Winbond [1], Nanya [2], and CXMT [3] devices. All three devices adopt the 7.8F2 DRAM cell layout, with active inclined at 69 degrees to the word line (WL). The DRAM feature size (F) is calculated from the unit cell area, which is the product of the WL pitch and bit line (BL) pitch (valid for the 7.8F2 DRAM cell layout). The active half-pitch (HP) is generally a few nanometers smaller than the DRAM feature size (F).
| Ref. | Foundry | Label | Active Pitch (nm) | WL Pitch (nm) | BL Pitch (nm) | Cell 7.8F2 (µm2) | Feature F (nm) |
| [] | Winbond | 20 nm | 40 | 56 | 64 | 0.00358 | 21.44 |
| [] | Nanya | 1B | 33.5 | 45.8 | 53.6 | 0.00245 | 17.74 |
| [] | CXMT | G4 | 29.5 | 41.7 | 47.9 | 0.002 | 16 |
Table 2.0.1: Comparison of most advanced devices from Winbond, Nanya, and CXMT. TechInsights, 2025.
Winbond 20 nm DRAM falls under D2z (third generation of the 20 nm class DRAM node), Nanya 1B DRAM is comparable to D1y (second generation of the 10 nm class DRAM node), and CMXT G4 DRAM is on par with D1z (third generation of the 10 nm class DRAM node).
| DRAM | Active HP (nm) | Cell 7.8F2 (µm2) | Feature F (nm) | |||||||||
| Node | Samsung | SK hynix | Micron | CXMT | Samsung | SK hynix | Micron | CXMT | Samsung | SK hynix | Micron | CXMT |
| D1x | 17 | 17 | 19 | 17 | 0.00253 | 0.00253 | 0.00328 | 0.00253 | 18.0 | 18.0 | 20.5 | 16.0 |
| D1y | 16 | 16 | 17 | - | 0.00225 | 0.00218 | 0.00239 | - | 17.0 | 16.7 | 17.5 | - |
| D1z | 15 | 15 | 15 | 15 | 0.00192 | 0.00200 | 0.00200 | 0.00200 | 15.7 | 16.0 | 16.0 | 15.0 |
| D1a | 13 | 14 | 14 | - | 0.00151 | 0.00176 | 0.00166 | 0.00176 | 13.9 | 15.0 | 14.6 | - |
| D1b | 12 | 12 | 12 | - | 0.00124 | 0.00126 | 0.00132 | - | 12.6 | 12.7 | 13.0 | - |
| D1c | - | - | - | - | 0.00100 | 0.00101 | 0.00107 | - | 11.3 | 11.4 | 11.7 | - |
| D1d | - | - | - | - | 0.00081 | 0.00083 | 0.00086 | - | 10.2 | 10.3 | 10.5 | - |
| D1d* | - | - | - | - | 0.00086 | 0.00088 | 0.00091 | - | 10.5 | 10.6 | 10.8 | - |
| D1e* | - | - | - | - | 0.00078 | 0.00080 | 0.00080 | - | 10.0 | 10.1 | 10.3 | - |
Table 2.0.2: 10 nm class DRAM nodes of Samsung, SK hynix, Micron, and CXMT. TechInsights, 2025.
TechInsights had analyzed five generations of 10 nm class DRAM nodes (D1x, D1y, D1z, D1a, D1b) from the three major vendors (Samsung, SK hynix, and Micron). The sixth generation (D1c), with a 10 % shrink, is around the DRAM feature size of 11 nm. The seventh generation (D1d) may continue as 10 % shrink or at a less aggressive scaling of 7 to 8 % shrink, allowing another generation (D1e) before conversion to 4F2 or 3D DRAM. Micron might be the only one to adopt D1e. CXMT had G1 (D2y), G3 (D1x), and G4 (D1z) available, and is likely to continue to skip some nodes to shorten the gap between itself and the other major vendors.
are you sure that 15.0 Feature F for CXMT in D1z is correct? The first table had it as 16 (and I believe that's the correct value).
Also, how did it get a 0.00176 µm2 Cell for CXMT if it hasn't examine a D1a product yet?
China's top memory chip maker YMTC to build 3rd plant, eyeing 2027 start
Total capital spending in 2025 on NAND to be 19B$ -> 20% -> 3.8B$
We can assume almost all that 4B$ will end up spent on local SME companies. That's a lot of money, almost like the full revenue of NAURA!
Last edited:
JCET Auto semiconductor packaging division covers China new AEB standard.
The Automatic Emergency Braking ( AEB ) system has officially entered a new phase of mandatory standard equipment globally, driven by both policy and market forces. China's Ministry of Industry and Information Technology released a draft national standard for public comment in April, proposing to mandate AEB for certain passenger cars and trucks starting in January 2028. Meanwhile , the United States and the European Union have also introduced similar regulations, comprehensively promoting AEB as a standard safety feature in new vehicles. Driven by both regulations and technology, the AEB market is experiencing explosive growth, bringing new opportunities to the entire automotive electronics industry chain.
JCET's Automotive Electronics Division explained that the AEB system integrates chips such as MCU, CIS, ISP, SerDes, MMIC, laser driver, ADC, point cloud processing, signal conditioning, MEMS sensing, motor driver, safety MCU, and CAN bus transceiver. Package types include TO series, SOP series, QFP, DFN/QFN, BGA, LGA, and SiP. Regarding packaging requirements, automotive chips typically need to operate normally within a temperature range of -40℃ to 125℃ (or even wider). Matching the coefficient of thermal expansion (CTE) of the packaging material is crucial to prevent internal connection breakage or package cracking due to temperature cycling. Simultaneously, the continuous vibration and impact during vehicle operation require the package to possess high mechanical stability and fatigue resistance, ensuring that internal chip connections do not fail due to long-term vibration. Furthermore, the automotive interior is a complex electromagnetic environment; therefore, the package needs to be resistant to electromagnetic interference while also minimizing electromagnetic radiation that could interfere with other devices.
These fabs are going to be built almost all domestic tools hopefully lithography is included.
Jufeng Semiconductor completes equity financing of hundreds of millions of yuan
Recently, Guangdong Jufeng Semiconductor Co., Ltd., a manufacturer of high-end power semiconductor chips, completed an equity financing round of several hundred million yuan. The investors in this round were Shenzhen Capital Group, Shenzhen Heavy Investment Group, Nanshan Strategic Investment Group, and Zeyi Capital.
According to public information, Jufeng Semiconductor was established in 2019, focusing on the R&D and manufacturing of driver ICs, PMICs, IPMs, and power modules. Its product range includes non-isolated driver ICs, isolated driver ICs, IPMs, power modules, PMICs, automotive-grade products, SiC, and GaN. Its non-isolated driver ICs utilize high negative voltage driving technology, adapting to various high-precision control scenarios. Its IPMs have undergone long-term mass application verification by leading industry customers, exhibiting low EMI and high immunity. Its automotive-grade products are all AEC-Q certified, integrating multiple protection functions and widely used in large appliances and industrial control fields. Investors include well-known institutions and enterprises such as Wuyuefeng Capital, SMIC Capital, Yuanhe Holdings, Guangzhou Industrial Investment Holding Group Co., Ltd., Shenzhen Capital Group, Inovance Technology, SAIC Motor, and BAIC Group.
According to public information, Jufeng Semiconductor was established in 2019, focusing on the R&D and manufacturing of driver ICs, PMICs, IPMs, and power modules. Its product range includes non-isolated driver ICs, isolated driver ICs, IPMs, power modules, PMICs, automotive-grade products, SiC, and GaN. Its non-isolated driver ICs utilize high negative voltage driving technology, adapting to various high-precision control scenarios. Its IPMs have undergone long-term mass application verification by leading industry customers, exhibiting low EMI and high immunity. Its automotive-grade products are all AEC-Q certified, integrating multiple protection functions and widely used in large appliances and industrial control fields. Investors include well-known institutions and enterprises such as Wuyuefeng Capital, SMIC Capital, Yuanhe Holdings, Guangzhou Industrial Investment Holding Group Co., Ltd., Shenzhen Capital Group, Inovance Technology, SAIC Motor, and BAIC Group.
Wafer-level Simultaneous Structuring Enables High-Precision V-Grooves for Next-Generation Photonic Packaging.
Optical Connections, a leading international media outlet dedicated to optical communication technologies, recently published a feature article authored by Focuslight in its Autumn 2025 issue, titled: “Wafer-level Simultaneous Structuring Enables High-Precision V-Grooves for Next-Generation Photonic Packaging”.
The article provides an in-depth discussion of how engineered V-groove structures are driving the evolution of next-generation photonic integrated circuit (PIC) fiber interfaces and systematically elaborates on the advantages of Focuslight’s wafer-level simultaneous structuring process in achieving submicron precision, scalability, manufacturing efficiency, and performance uniformity.
Key Insights
1. Limitations of Traditional V-Groove Fabrication
As the number of channels in photonic integrated circuits (PICs) continues to grow, mechanical dicing or tool-based V-groove processes face increasing challenges in maintaining groove depth uniformity, pitch deviation, and positional error. These limitations make it difficult to meet the stringent alignment and coupling precision requirements of advanced optical packaging.
2. Breakthrough Through Wafer-level Simultaneous Structuring
Focuslight’s wafer-level simultaneous structuring technology eliminates cumulative errors inherent to sequential machining, enabling simultaneous formation of multiple V-grooves with submicron alignment accuracy. This approach ensures performance consistency, high yield, and consistent optical coupling performance, representing a scalable and high-precision manufacturing solution for next-generation optical packaging.
3. Enabling Next-Generation Optical Interconnects
With continuous advancements in wafer-level microfabrication and metrology, Focuslight is advancing optical packaging technologies toward greater reliability and mass-production readiness, meeting the rising demands of telecommunication networks, data centres and AI computing for high-bandwidth and energy-efficient photonic interconnects.
True to its motto – Engineered in Europe, Scaled in Asia – Accelerating Global Reach in High-Precision Micro-Optics – Focuslight continues to deliver innovative and practical solutions that address the challenges of next-generation networks, empowering our customers to advance the future of the optical communications.
The article provides an in-depth discussion of how engineered V-groove structures are driving the evolution of next-generation photonic integrated circuit (PIC) fiber interfaces and systematically elaborates on the advantages of Focuslight’s wafer-level simultaneous structuring process in achieving submicron precision, scalability, manufacturing efficiency, and performance uniformity.
Key Insights
1. Limitations of Traditional V-Groove Fabrication
As the number of channels in photonic integrated circuits (PICs) continues to grow, mechanical dicing or tool-based V-groove processes face increasing challenges in maintaining groove depth uniformity, pitch deviation, and positional error. These limitations make it difficult to meet the stringent alignment and coupling precision requirements of advanced optical packaging.
2. Breakthrough Through Wafer-level Simultaneous Structuring
Focuslight’s wafer-level simultaneous structuring technology eliminates cumulative errors inherent to sequential machining, enabling simultaneous formation of multiple V-grooves with submicron alignment accuracy. This approach ensures performance consistency, high yield, and consistent optical coupling performance, representing a scalable and high-precision manufacturing solution for next-generation optical packaging.
3. Enabling Next-Generation Optical Interconnects
With continuous advancements in wafer-level microfabrication and metrology, Focuslight is advancing optical packaging technologies toward greater reliability and mass-production readiness, meeting the rising demands of telecommunication networks, data centres and AI computing for high-bandwidth and energy-efficient photonic interconnects.
True to its motto – Engineered in Europe, Scaled in Asia – Accelerating Global Reach in High-Precision Micro-Optics – Focuslight continues to deliver innovative and practical solutions that address the challenges of next-generation networks, empowering our customers to advance the future of the optical communications.