Chinese semiconductor thread II

interestedseal

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Yet another euv source startup working on a modified version of Harbin’s DPP tech. Even if not powerful enough for litho, this could still work for euv inspection and metrology. So far I’ve counted at least 5 teams working on euv light source from open source info alone, so I’m guessing there’s even more beneath the surface
 

BoraTas

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What are the issues you see with HBM3 and what are the bottlenecks facing China?
It requires 1-alpha DRAM process. CXMT very recently achieved 1z. 1-alpha is one node ahead of 1z. There is also no HBM of any kind from China until now, which understandable as making HBM versions below HBM2E would not make commercial sense. HBM2E is now possible with 1z but it wasn't possible with 1x which was where CXMT was. I believe 1z is why we started to hear about HBM recently.
 

tphuang

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Chips designed for embarrassingly parallel workloads like AI have their yields not strongly affected by chip size. Such chips has so much duplication that faults are usually either inconsequential or can be isolated away after testing. In fact, extra size sometimes mean a higher yield if the reason for the added size is sections to improve the yield like redundant logic, fuses to isolate faulty parts etc... They wrote about Cerebras' wafer scale chip on this thread. The production yield for that chip is 100% despite its size of 46225 mm2. For consumer CPUs, it is a different matter. Those chips don't have much independent sections or logic redundancy. Chiplets were also about cutting design costs for AMD, not just for cutting fabbing costs. They generated a lot of CPUs from a few designs. Have you ever wondered why they didn't apply their chiplet expertise to their lowly performing GPU products until the end of 2022? Size simply doesn't matter much for GPU yields.
Regardless of D0 for something like AI chip, finding 50 400mm2 good dies on a wafer is easier than finding 25 800mm2 good dies.

At best, we can say that yield for Ascend will be significantly better than yield of a complicated SoC of same size.

I can't really speak for Cerebras chip. Maybe they can tolerate 2% of transistors not working. Given that SMIC will have much higher D0 than TSMC, tolerance for faulty transistors on ascend chips will have to be a lot higher

Even just the below the table gravepine talk I've heard, the yield on Ascend chips just isn't great
 

tphuang

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It requires 1-alpha DRAM process. CXMT very recently achieved 1z. 1-alpha is one node ahead of 1z. There is also no HBM of any kind from China until now, which understandable as making HBM versions below HBM2E would not make commercial sense. HBM2E is now possible with 1z but it wasn't possible with 1x which was where CXMT was. I believe 1z is why we started to hear about HBM recently.
looks like they are finally making good progress with D1z and are looking to do LPDDR5x with D1z. But even with that, I think mass production probably is more like 2025 type of thing. If they can get 17nm/LPDDR5 in mass production this year for smart phone OEMs, that would be pretty good progress vs what they did before
 

BoraTas

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looks like they are finally making good progress with D1z and are looking to do LPDDR5x with D1z. But even with that, I think mass production probably is more like 2025 type of thing. If they can get 17nm/LPDDR5 in mass production this year for smart phone OEMs, that would be pretty good progress vs what they did before
Didn't they advertise DDR5 for this year? 1z is needed to call a DRAM module DDR5.
 

LanceD23

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developing 5nm, 3nm using DUV, that's against conventional wisdom. it's more than multi patterning.
It's using corrective weird scheme on layout side(emphasize sharp edges around corners and turns) to compensate DUV limitation so the final outcome looks correct.
 

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european_guy

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It requires 1-alpha DRAM process. CXMT very recently achieved 1z. 1-alpha is one node ahead of 1z. There is also no HBM of any kind from China until now, which understandable as making HBM versions below HBM2E would not make commercial sense. HBM2E is now possible with 1z but it wasn't possible with 1x which was where CXMT was. I believe 1z is why we started to hear about HBM recently.

This is quite interesting info. Thanks.

Just for reference
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, while HBM3 is used by NVIDIA H100, memory bandwidth is double.

First HBM2E chip came out in 2019, while HBM3 in 2022.

For Huawei getting HBM3 chips can be a problem, but currently US has still not banned HBM memory for export to China, so Alibaba, Tencent, China Mobile, etc can stockpile HBM3 memory and then provide (not sell) them to Huawei to mount on the Ascend boards for their own use. These AI boards are customized for data centers and are not for general public, each customer get its own board eventually providing its own components.

SK Hynix
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recently that HBM memory demand is huge...maybe not only due to Nvidia:
SK Hynix's advanced DRAM chips such as high bandwidth memory (HBM) chips are in high demand for use in the graphic processing units (GPUs) made by Nvidia and others that process vast amounts of data in generative AI.
The company said its sales of HBM3 chips - which it developed ahead of rivals - increased by more than fivefold in 2023 from a year earlier.

I would expect HBM3 stockpiling is ongoing now in China....US can close this loophole at any time, applying some pressure on Korean government, so better buy now while waiting for CXMT.

I can't really speak for Cerebras chip. Maybe they can tolerate 2% of transistors not working. Given that SMIC will have much higher D0 than TSMC, tolerance for faulty transistors on ascend chips will have to be a lot higher

Even just the below the table gravepine talk I've heard, the yield on Ascend chips just isn't great

Maybe this requires a new design....Cerberas can tolerate not working transistors because they have designed in the needed redundancy / isolation of defected cores. New Ascend chip version, designed for SMIC process (not TSMC as the old one), can somehow improve robustness to defects and so increasing effective yield, i.e. the number of working chips per wafer although with less cores and/or limited frequency...
 

gelgoog

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These large highly regular chips, like @BoraTas said, can have fuses built into the design. After the wafer is manufactured the chips get inspected. Any non-functioning blocks, due to manufacturing errors, can then be disabled by cutting the fuses. This can be done with a laser. So you can still get an operational chip despite it being rather large in area. Chips with less functional blocks can be binned as lower performance models. So for example you get GPU chips with more or less functional "cores".

Only if the chip manufacturing error is in one of the non-replicated blocks, like in the chip I/O, would that chip be a total writeoff.
 
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