Chinese semiconductor thread II

GiantPanda

Junior Member
Registered Member
While the media is still buzzing about Huawei joining hands with Semiconductor Manufacturing International (SMIC) to manufacture advanced process 7nm and even 5nm chips, on the same day that TSMC held its 2024 Technology Forum in Hsinchu, China's 26th IC Manufacturing Annual Conference and Supply Chain Innovation Forum was also held in Guangzhou during May 22-24.

Ye Tianchun, President of the Integrated Circuit Branch of the China Semiconductor Industry Association and Vice President and Secretary-General of the China Integrated Circuit Innovation Alliance delivered a keynote speech on "Path Innovation and Leapfrog Development" in the Chinese IC industry at the opening ceremony of the conference, highlighting the importance of continuous innovation to upgrade technologies at the mature nodes.

Ye analyzed the current state of development in China's IC industry across design, manufacturing, packaging and testing, equipment, materials, and components through various sets of industrial data. He pointed out five major blind spots in the Chinese industry, expressing concern that within 3 to 5 years, Chinese chips might regress to mid-to-low-end levels, worsening the situation.

He noted that the development approach of China's IC industry over the past decade has primarily been focused on "catching up with existing technological paths" and addressing "shortcomings." While this method allows for easy catch-up and fewer detours, it also risks falling into "path dependency," resulting in technological lag and a passive stance.

In this regard, Ye Tianchun believes that from a strategic perspective, "path dependency" is the biggest obstacle to the Chinese IC industry advancing to higher levels. Particularly on traditional technological paths, China's progress in advanced processes is being fully obstructed. If China cannot forge a new path, there is a risk of regressing to mid-to-low-end levels within 3 to 5 years.

Focusing on back-end and mature-node innovations​

He emphasized that the external pressures will compel the Chinese IC industry to innovate its paths 7 to 8 years ahead of the global semiconductor industry.

As Moore's Law approaches its physical limits at 2nm and 3nm, the global industry is considering innovations in product architecture. However, China needs to consider architectural innovation before reaching 7nm, which is why 3D system packaging has become so prominent in recent years.

Particularly, the difficulties encountered by China in front-end processes such as advanced wafer manufacturing will force China to innovate in back-end processes such as packaging and testing, creating opportunities for 3D heterogeneous integration system packaging, FDSOI, and FinFET technologies.

However, when discussing the "path innovation strategy," industry insiders in China often fall into common cognitive blind spots. Ye Tianchun pointed out that one such blind spot is China's 3D system packaging being detached from product design architecture innovation, which is like trying to innovate behind closed doors.

Chiplets have become very popular in the semiconductor industry, but their essence lies in system packaging. To achieve this, the focus should not be on the processing side but on the design side, requiring cooperation between IC designers and application system manufacturers with semiconductor packaging and testing companies to form solutions based on product architecture innovation, said Ye.

Ye Tianchun directly pointed out another common blind spot inside and outside the Chinese industry, which is focusing solely on so-called "advanced processes" while ignoring "mature process" innovative features. He emphasized that developing special processes within mature processes to advance from mid-to-low end to high-end is a critical task for path innovation.

Since the equipment and technologies for producing advanced nodes are under export control by the United States, China's opportunities are in the mature and legacy nodes. With dozens of new fabs being built in China to produce mature chips to increase output significantly in the next few years, China needs to upgrade the quality of its chips to gain market dominance. Otherwise, the oversupply of low-quality mature chips will result in a vicious cycle of cut-throat price competition among local producers.

Nice article, the headline notwithstanding.

In so many words, CSIA chief Ye Tianchun wants China to innovate and leap frog instead of following established methods. He wants the industry to look to innovate new processes for mature nodes not just pursue the leading edge only.

The proper road map for an industry with such depth and breadth that shouldn't just try to replicate the same processes that the West is trying to block you in but to advance beyond them with difference approaches.

The crux of the speech and article:

Ye Tianchun, President of the Integrated Circuit Branch of the China Semiconductor Industry Association and Vice President and Secretary-General of the China Integrated Circuit Innovation Alliance delivered a keynote speech on "Path Innovation and Leapfrog Development" in the Chinese IC industry at the opening ceremony of the conference, highlighting the importance of continuous innovation to upgrade technologies at the mature nodes.
 

mst

Junior Member
Registered Member
These performance issues, combined with Nvidia's abundant supply and sanctions restrictions, have forced it to cut H20 prices by "over 10 percent" in the Chinese market. One of the companies noted in the original story that still supports Nvidia in China is the online marketplace Alibaba, which ordered over 30,000 Nvidia H20 chips. Distributors are selling the H20 at roughly 100,000 yuan, compared to the Huawei 910B, which can exceed 120,000 yuan per card.
 

tokenanalyst

Brigadier
Registered Member
For EUV, does 5nm require multiple patterning or just once?
Still multiple patterning, there are statistical effects that make difficult the pattern of features using single patterning EUV, this effects are accentuated by the dosage, because in lithography you have balance speed with the light energy dose, the higher the dose the better the pattern because more photons hit the intended target but affects the speed and reverse more speed better costs. time is literally money here. So seems that multiple patterning is here to stay. Maybe in the future with FEL, SSMB and others due their high power would be possible to make pattern is a single step. Hopefully, crossing fingers, because litho is getting too expensive for consumer electronics.

1716656878687.png

There is a reason why Intel decided to go with HNA EUV even with reduced mask size , they don't how to deal with statistical errors in EUV lithography so they prefer stitching chip patterns than dealing with Multiple patterning EUV.
TSMC in the other hand seems that they prefer multiple patterning that dealing with a reduce mask size and stitching.
 

Hyper

Junior Member
Registered Member
Still multiple patterning, there are statistical effects that make difficult the pattern of features using single patterning EUV, this effects are accentuated by the dosage, because in lithography you have balance speed with the light energy dose, the higher the dose the better the pattern because more photons hit the intended target but affects the speed and reverse more speed better costs. time is literally money here. So seems that multiple patterning is here to stay. Maybe in the future with FEL, SSMB and others due their high power would be possible to make pattern is a single step. Hopefully, crossing fingers, because litho is getting too expensive for consumer electronics.

View attachment 130112

There is a reason why Intel decided to go with HNA EUV even with reduced mask size , they don't how to deal with statistical errors in EUV lithography so they prefer stitching chip patterns than dealing with Multiple patterning EUV.
TSMC in the other hand seems that they prefer multiple patterning that dealing with a reduce mask size and stitching.
Not really. EUV is ionising radiation so power can't be increased beyond a certain limit. Electrons in the resist are a pain. And there doesn't seem to be any workaround. The best would be a better pair to resist but as it stands lithography enabled scaling will run out of steam by 2035-40 with hyper-na euv if it's built.
 
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