Break ARM's monopoly! China releases the world's first open source large-scale on-chip interconnection network IP "Wenyu River" to build a chip core bridge
on May 23 that Beijing Open Source Chip Research Institute (hereinafter referred to as "Open Source Institute") officially announced today that on May 21, 2024, Open Source Institute officially released the world's first open source large-scale on-chip Internet network (Network on Chip, NoC) IP to its member units through an online meeting - R&D codenamed "Wenyu River" . This major breakthrough marks that Open Source Institute has taken a solid step in promoting the development of data center server chip technology.
It is reported that NoC is the core basic IP for data center server chips in addition to high-performance processor cores. Currently, there is only one supplier in the world, ARM, which restricts the use of RISC-V processor cores to a certain extent .
Since the establishment of the project, Kaixin Institute has successfully completed the development and verification of NoC IP supporting 64-core interconnection after 18 months of intense development. Currently, this NoC IP can be delivered to enterprises for evaluation , further promoting the development of the RISC-V ecosystem.
As a result, OpenCore can provide the most important core basic IP for data center server CPU chips, the "Xiangshan" high-performance processor core and the "Wenyu River" large-scale on-chip interconnect network . This is also the first time in the world that the construction of a data center server CPU chip can be completed based on an open source project.
The conference attracted about 100 engineers from more than 20 RISC-V chip companies across the country.
Beijing and the Chinese Academy of Sciences organized a group of domestic industry-leading companies and top scientific research institutions to establish the OpenCore Institute on December 6, 2021 to develop the RISC-V ecosystem. The OpenCore Institute is committed to accelerating the integration of the RISC-V innovation chain and the industrial chain, striving to initially build an open source chip technology system by 2025, and become the world's leading RISC-V industry ecosystem center by 2030.
Bao Yungang, a researcher at the Institute of Computing Technology of the Chinese Academy of Sciences and the main person in charge of the "Xiangshan" RISC-V open source processor, said:-
High-end processor chips contain two core IPs: one is the CPU Core responsible for calculations, such as the V1/N1/V2/N2 cores of the ARM Neoverse series; the other is the on-chip network that interconnects dozens or hundreds of processor cores. NoC (Network on Chip) can be regarded as the bridge within the chip, such as ARM CMN-600/700 series IP.
The "Xiangshan" high-performance RISC-V processor core is the first type of IP mentioned above. It has now developed to the third generation and its performance can reach ARM N2. It was just released at the Zhongguancun Forum some time ago. However, for the second type of NoC IP, especially the single-chip 100-core NoC, currently only the ARM CMN series is available in the world (there is no example of the Arteris FlexNoC series yet), and the single license price is as high as hundreds of millions of RMB, and there are many restrictions .
The design and implementation of large-scale on-chip interconnection networks (NoCs) are extremely difficult (especially cache consistency issues), and have become the shortcoming of the global RISC-V ecosystem. In order to change this situation, in 2022, OpenCore launched the first-generation NoC "Wenyu River" project, led by Professor Wang Qi, and supported by many companies. After 18 months of research and development, the development and verification of NoC IP supporting 64-core interconnection has been successfully completed, and it was released online on May 21. About 100 engineers from more than 20 RISC-V chip companies across the country participated, which attracted widespread attention.
Now the research and development work of the second generation NoC has also started , which will form a closer adaptation and optimization with the "Xiangshan" core, and better support the interconnection and expansion of AI accelerators. Looking forward to more corporate support and participation.
