DUVs are already being built by SMEE, what they are still doing to ramping up enougn production to meet domestic needs. The EUV prototype should be mostly complete at this point and in use by SMIC by next year. A lot of posts you see now in this thread for Chinese EUV are companies setting up production for materials and components, which speaks well to the progress they are making towards commercialisation and volume production.
Chinese semiconductor thread II
- Thread starter vincent
- Start date
The coming together of the patent and supply chains for EUV have been very methodical. You can see that from this thread.
CETC here is making the various chips used in Chinese satellites
55th institute makes the power amplifier chips + microwave & MMW chips.
9th does a variety of high power devices
43rd does power suppliers
21st does solar array drives & laser communication
BYD Semiconductor made a presentation today of its chip portfolio. It claims to have chips that cover 80% of all auto grade chips. Now, even if the actual % is lower than that, you can see the 10% self sufficiency claims by Nikkei are complete nonsense
Not saying you are wrong, just not too sure how the percentage is measured… by number? Cost…?
A programmable topological photonic chip
Abstract
Controlling topological phases of light allows the observation of abundant topological phenomena and the development of robust photonic devices. The prospect of more sophisticated control with topological photonic devices for practical implementations requires high-level programmability. Here we demonstrate a fully programmable topological photonic chip with large-scale integration of silicon photonic nanocircuits and microresonators. Photonic artificial atoms and their interactions in our compound system can be individually addressed and controlled, allowing the arbitrary adjustment of structural parameters and geometrical configurations for the observation of dynamic topological phase transitions and diverse photonic topological insulators. Individual programming of artificial atoms on the generic chip enables the comprehensive statistical characterization of topological robustness against relatively weak disorders, and counterintuitive topological Anderson phase transitions induced by strong disorders. This generic topological photonic chip can be rapidly reprogrammed to implement multifunctionalities, providing a flexible and versatile platform for applications across fundamental science and topological technologies.
Last edited:
Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
Abstract
Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching,,,,,,,,,. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics,,, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.Up to 15 million yuan! Project Guidelines for Major Research Plans for Basic Research on New Devices in the Post-Moore Era Released
The National Natural Science Foundation of China released the “2024 Project Guidelines for the Major Research Program for Basic Research on New Devices in the Post-Moore Era”.
According to reports, this major research program is aimed at the country's major strategic needs for independent chip development, with basic chip issues as the core. It aims to develop new devices and computing architectures in the post-Moore era, break through the bottleneck of chip computing power, promote the improvement of my country's chip research level, and support my country's scientific and technological innovation in the chip field.
1. Scientific Objectives
This major research plan is aimed at the future chip computing power issues and focuses on the forefront of chip development. It plans to make breakthroughs in new mechanisms of ultra-low energy information processing, new mechanisms of carrier approximate ballistic transport, new materials with high mobility and high state density, new methods of high-density integration, and new non-von Schroeder computing architectures through the cross-integration of multiple disciplines such as information, mathematics, physics, materials, engineering, and life. It aims to develop ultra-low power devices with switching energy consumption below 1fJ and high-performance devices that exceed the carrier transport speed limit of silicon-based CMOS, achieve non-von Schroeder architecture chips with a computing power increase of more than 2 orders of magnitude, develop transformative basic devices, integration methods, and computing architectures, cultivate a research team with international influence, and enhance my country's independent innovation capabilities and international status in the chip field.
2. Core scientific issues
In view of the computing power bottleneck of chip technology in the post-Moore era, research is conducted around the following three core scientific issues:
1. Energy consumption boundary and breakthrough mechanism of CMOS devices.
It is necessary to focus on solving the following key issues: exploring the energy consumption boundary of single information processing by CMOS devices, studying new mechanisms to break through this boundary, and realizing data calculation, storage and transmission under ultra-low energy consumption.
(ii) Device mechanism that breaks through silicon-based speed limits.
It is necessary to focus on solving the following key issues: on the basis of exploring new material systems with both long free path of carriers and high density of states, study the device mechanism of approximate ballistic transport, and realize high-performance devices that break through the silicon-based carrier speed limit .
(3) A mechanism that surpasses the energy efficiency of the classic von Neumann architecture.
The following key issues need to be addressed: exploring the mechanisms and methods for the integration of computing and storage, and combining new information coding paradigms to realize new computing architectures and break through the energy efficiency bottleneck of the von Neumann architecture.
3. Key research directions for funding in 2024
1. Cultivation projects
Focusing on the above scientific issues and guided by the overall scientific goals, we plan to fund five cultivation projects with strong exploratory nature, novel topics, and good preliminary research foundation. The research directions include but are not limited to the following:
1. Theory, materials and integration technology of ultra-low power devices.
Aiming at the switching energy consumption target of less than 1fJ, research on new principle logic, memory devices and their core materials and integration technologies beyond CMOS; research on extremely low-power information processing and storage mechanisms and models under extreme physical conditions.
2. Theory, materials and integration technology of high-speed and high-performance devices.
Explore the ballistic transport mechanism, seek new silicon-based compatible semiconductor materials with high mobility and high density of states, research and realize new field effect devices with high ballistic transport coefficients; explore high-speed information processing, access and transmission under limited energy consumption New mechanisms and their device technologies.
3. Highly energy-efficient computing and storage architecture.
Explore new computing architectures and storage architectures that break through the von Neumann energy efficiency bottleneck, and study design methodologies for new architectures for in-memory computing.
Key Support Projects
1. Ballistic Transport Devices at Ultra-Low TemperaturesDevelop low-power, high-performance devices operating below 77K, achieving ultra-high current switching ratios and ballistic transport coefficients, with carrier injection speeds exceeding 1×10^7 cm/s. Establish a PDK for low-temperature devices, design, and verify an 8-bit microprocessor, demonstrating superior speed and power efficiency.
2.High Mobility Stacked Channel Gate-All-Around CMOS Device
Create a high-performance CMOS device with a stacked channel structure of at least 3 layers, achieving high on-state currents for both NMOS and PMOS transistors at 0.7 V, with a threshold voltage deviation of less than 100 mV and a switching ratio over 10^6.
3.Highly Robust SRAM Storage and Computing Integrated Architecture
Design a robust SRAM-based storage and computing architecture with high computing power density for various precisions, achieving a single-chip computing power of at least 4 TOPS, supporting mainstream computing precisions, and addressing scalability for large models with computing power not less than 100 TOPS@INT8, 50 TFLOPS@BF16.
4.Heterogeneous Storage and Computing Integrated Architecture
Integrate non-volatile and volatile memories into a flexible programmable architecture, achieving high energy efficiency (>20 TOPS/W@INT8) and supporting various AI algorithms and large models.
5.High-Precision Simulation Computing Architecture for Scientific Computing
Develop an analog computing architecture for scientific computing or AI for Science, solving linear and nonlinear matrix equations, and differential equations with a scale of at least 1024×1024 and accuracy of no less than 32-bit floating point, aiming for 2 orders of magnitude reduction in power consumption and 1 order of magnitude reduction in solution delay compared to FP32.
6.Heterogeneous Many-Core Architecture Design Methods for New Computing Devices
Establish a design methodology for heterogeneous many-core architectures tailored to new computing devices, including automated generation and optimization methods, targeting a dedicated computing power of at least 64 TOPS@INT8 and a general computing power of no less than 6 TOPS@INT8.
(3) Integration projects.
It is planned to select three integrated projects with significant application value and good research foundation for funding. The directions are as follows:
1. Two-dimensional semiconductor technology for large-scale CMOS integration.
In response to the demand for ultra-low power devices in the post-Moore era, we study single-atom-layer two-dimensional semiconductor materials, devices, EDA and processes for large-scale CMOS integration to solve the bottlenecks of miniaturization and power consumption faced by silicon-based CMOS technology. Develop methods for preparing N-type and P-type two-dimensional semiconductor single crystals to achieve the preparation of continuous thin films of two-dimensional semiconductor single crystals on 8-inch silicon-based substrates; we study the integration process of two-dimensional semiconductor devices to achieve CMOS logic gate units based on two-dimensional semiconductors, where the device gate dielectric equivalent oxide layer thickness (EOT) is ≤1 nm, the ohmic contact resistance is ≤100 Ω·μm (contact length ≤20 nm), and the on-state current density is ≥1 mA/μm at 1 V source-drain voltage; we develop device-process-circuit collaborative optimization strategies to develop thousand-gate-level two-dimensional semiconductor logic chips to achieve key logic function verification.
2. RISC-V and storage and computing heterogeneous fusion chip.
Aiming at the needs of high computing density, computing completeness, and autonomous and controllable ecology for artificial intelligence applications such as large models, we study the design of heterogeneous fusion architecture of SRAM storage and computing and high-performance RISC-V processors, multi-core scalable architecture and high-speed interconnection design, and full-stack heterogeneous computing compilation and software stack. We have completed the storage and computing extension instruction set based on high-performance RISC-V processor cores, including no less than 10 extension instructions, and realized a prototype of heterogeneous computing chip. The computing density of AI computing modules is greater than 5.92 TPP/mm2. We have completed the design of multi-core heterogeneous scalable computing architecture and its simulator, with the computing power of the architecture being no less than 100 TOPS@INT8. We have completed the RISC-V heterogeneous compilation full-stack software tool chain, and realized efficient compilation and automated program deployment for heterogeneous multi-core chips.
3. Data-driven storage and computing integrated computing architecture.
Aiming at the high computing power and high energy efficiency requirements of artificial intelligence, we study the storage-computing integrated computing architecture that combines data-driven digital computing with in-memory computing and develop verification chips. We study the data encoding method and computing principle of the storage-computing integrated architecture, explore data-driven storage-computing collaborative data flow, design circuits, system architectures and parallel methods that are suitable for storage-computing integration, and solve the difficult problem of high energy efficiency, high precision and high flexibility in intelligent computing chips. We develop data-driven storage-computing integrated computing chips that support variable computing precision, support >10 linear and nonlinear operators, peak computing energy efficiency >40 TOPS·bit/W, storage-computing array performance density >12 TOPS·bit/mm 2 , storage capacity >1 Mb, storage density >1 Mb/mm 2 , and complete verification on typical artificial intelligence models.
It is planned to select three integrated projects with significant application value and good research foundation for funding. The directions are as follows:
1. Two-dimensional semiconductor technology for large-scale CMOS integration.
In response to the demand for ultra-low power devices in the post-Moore era, we study single-atom-layer two-dimensional semiconductor materials, devices, EDA and processes for large-scale CMOS integration to solve the bottlenecks of miniaturization and power consumption faced by silicon-based CMOS technology. Develop methods for preparing N-type and P-type two-dimensional semiconductor single crystals to achieve the preparation of continuous thin films of two-dimensional semiconductor single crystals on 8-inch silicon-based substrates; we study the integration process of two-dimensional semiconductor devices to achieve CMOS logic gate units based on two-dimensional semiconductors, where the device gate dielectric equivalent oxide layer thickness (EOT) is ≤1 nm, the ohmic contact resistance is ≤100 Ω·μm (contact length ≤20 nm), and the on-state current density is ≥1 mA/μm at 1 V source-drain voltage; we develop device-process-circuit collaborative optimization strategies to develop thousand-gate-level two-dimensional semiconductor logic chips to achieve key logic function verification.
2. RISC-V and storage and computing heterogeneous fusion chip.
Aiming at the needs of high computing density, computing completeness, and autonomous and controllable ecology for artificial intelligence applications such as large models, we study the design of heterogeneous fusion architecture of SRAM storage and computing and high-performance RISC-V processors, multi-core scalable architecture and high-speed interconnection design, and full-stack heterogeneous computing compilation and software stack. We have completed the storage and computing extension instruction set based on high-performance RISC-V processor cores, including no less than 10 extension instructions, and realized a prototype of heterogeneous computing chip. The computing density of AI computing modules is greater than 5.92 TPP/mm2. We have completed the design of multi-core heterogeneous scalable computing architecture and its simulator, with the computing power of the architecture being no less than 100 TOPS@INT8. We have completed the RISC-V heterogeneous compilation full-stack software tool chain, and realized efficient compilation and automated program deployment for heterogeneous multi-core chips.
3. Data-driven storage and computing integrated computing architecture.
Aiming at the high computing power and high energy efficiency requirements of artificial intelligence, we study the storage-computing integrated computing architecture that combines data-driven digital computing with in-memory computing and develop verification chips. We study the data encoding method and computing principle of the storage-computing integrated architecture, explore data-driven storage-computing collaborative data flow, design circuits, system architectures and parallel methods that are suitable for storage-computing integration, and solve the difficult problem of high energy efficiency, high precision and high flexibility in intelligent computing chips. We develop data-driven storage-computing integrated computing chips that support variable computing precision, support >10 linear and nonlinear operators, peak computing energy efficiency >40 TOPS·bit/W, storage-computing array performance density >12 TOPS·bit/mm 2 , storage capacity >1 Mb, storage density >1 Mb/mm 2 , and complete verification on typical artificial intelligence models.