Peking University's School of Integrated Circuits/Advanced Innovation Center for Integrated Circuits has upgraded its AI for EDA open-source dataset CircuitNet to version 3.0.
The CircuitNet series of open-source datasets for AI for EDA, long promoted by the research group of Professor Yibo Lin and Professor Runsheng Wang at Peking University, has now been upgraded to version 3.0. Previously, the research group, in collaboration with other researchers, released CircuitNet 1.0 , addressing the lack of public datasets in the AI for EDA field by constructing the first large-scale open-source EDA dataset. This provided a standardized data foundation for research on machine learning methods in chip design tasks, and the related results were published in *Science China: Information Sciences* , with extended work published in *IEEE TCAD *. Subsequently, the team further proposed CircuitNet 2.0 , expanding the data scale, design tasks, and evaluation benchmarks for advanced processes and more realistic chip design scenarios; the related paper was accepted for ICLR 2024. Recently, in collaboration with the team at the Institute of Computing Technology, Chinese Academy of Sciences, they proposed a new generation of open-source datasets for AI-driven chip design, CircuitNet 3.0 . The related paper, jointly completed by the Institute of Computing Technology, the School of Integrated Circuits at Peking University, and the Chinese University of Hong Kong, was published at ICLR 2026, a top international machine learning conference, providing important support for research and evaluation of machine learning methods in the field of chip design automation.
Building upon the work of its predecessors, CircuitNet 3.0 further expands the diversity of RTL designs, cross-stage data alignment, and multimodal joint modeling. Starting with validated open-source RTL designs, this work combines industrial-grade EDA workflows to generate netlists, placements, and performance metrics, and proposes task-oriented data augmentation and filtering methods: in the RTL stage, structured rewriting based on Verilog syntax trees enhances design diversity; in the netlist and physical design stages, samples with greater engineering value are filtered around timing and power prediction tasks. Through these methods, CircuitNet 3.0 not only expands the data scale and design coverage but also enhances its support for early timing/power prediction, cross-abstraction layer modeling, and multimodal AI for EDA research, demonstrating the continuous evolution of the CircuitNet series from backend task datasets to a full-process chip design data infrastructure.
Since its release, the CircuitNet series of works has received widespread attention from academia and industry. As the first large-scale open-source EDA dataset, CircuitNet provides an open and reproducible benchmark platform for AI for EDA research. The project homepage is: . Currently, the CircuitNet GitHub repository has received a large number of stars and has attracted attention and use from well-known companies and universities, including NVIDIA and Stanford University.
