Then it cannot be CXMT since CXMT has no LPDDR5X
Chinese semiconductor thread II
- Thread starter vincent
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Then it cannot be CXMT since CXMT has no LPDDR5X
hmm, that's not how things work. It's the same process and you would expect it to continue to improve in yield over time
as I explained earlier, big change in CPU architecture. Possibly going to 8 wide on core.
I read the original source on this. I think it's better to wait until the CPU comes out. He can be a little iffy.
Yep and people should remember this
progress of Horizon Robotics is very impressive. If you look at this link here
you can just see all the customers that have now signed up to Journey 6. A whole bunch of tier 1s also.
In terms of what they've done in chip design and software, they can get into other type of AI chips after this.
you can just see all the customers that have now signed up to Journey 6. A whole bunch of tier 1s also.
In terms of what they've done in chip design and software, they can get into other type of AI chips after this.
If Pura 70 doesn't use LPDDR5X，it's very unlikely it can achieve better benchmark score than Mate 60 pro
They changed the core architecture. It’s a very big change. Gpu firmware also really improved.
It is kind of annoying there is no proper information out there in free sources yet with regards to the Huawei Pura. We still don't have pictures of the SoC die. We still don't know exactly what's on the die and I have seen conflicting information with regards to the chips in the phone.
Interesting if Huawei can reach apple's M1 max level of performance i might consider to buy Matebook pro again when i need to replace my macbook in a couple of year.
Microelectronics has made new progress in the research of high-density and low-stress through silicon vias (TSV)
Recently, the team of researcher Jiao Binbin from the Microsystem Technology Laboratory of the New Technology Development Department of the Institute of Microelectronics has made new progress in the research of high-density and low-stress through silicon vias (TSV).
Three-dimensional (3D) integration technology is an essential technology for manufacturing low-power, high-performance and high-integration-density devices, and is expected to break through the limitations of Moore's Law. As a core technology for 3D integration, TSV has the advantages of shortening interconnection paths and reducing package size. Currently, high-density TSV interconnects are used in near-sensor and in-sensor computing, hybrid memory cubes, high-bandwidth memory (HBM), complementary metal-oxide semiconductor (CMOS) image sensors, cooled and uncooled focal plane arrays, active pixel sensors, and more It has important application prospects. However, in high-density application scenarios, due to the mismatch in thermal expansion coefficients between the silicon substrate and the TSV interconnection metal, TSVs have serious thermal stress problems, which will cause transistor mobility and parameter shifts to affect device performance and even cause device damage. , it is urgent to suppress the impact of thermal stress on device reliability through structural regulation.
Jiao Binbin's team innovatively proposed a "football-like" TSV structure that is narrow at both ends and wide in the middle, closed at both ends and hollow in the middle. It has the characteristics of small aperture, high aspect ratio, and low stress. The inwardly collapsing stress-buffering hollow structure provides stress relief space for TSV, which can significantly reduce the stress and electromigration of the substrate silicon. It can withstand large temperature difference operating conditions. The sealing structure at both ends is compatible with the subsequent traditional spin coating process. , has universal applicability. At present, the TSV structure with the largest depth (>100μm), the largest aspect ratio (>20.3:1), and the smallest residual stress (31.02MPa) reported internationally has been achieved. Its diameter is 5μm, the center distance is 25μm, and the number of TSVs reaches 320,000. (Density 1600/mm 2 ), effective connectivity rate reaches 100%, and is the only TSV solution that can withstand extremely low temperature conditions (-200°C).
Three-dimensional (3D) integration technology is an essential technology for manufacturing low-power, high-performance and high-integration-density devices, and is expected to break through the limitations of Moore's Law. As a core technology for 3D integration, TSV has the advantages of shortening interconnection paths and reducing package size. Currently, high-density TSV interconnects are used in near-sensor and in-sensor computing, hybrid memory cubes, high-bandwidth memory (HBM), complementary metal-oxide semiconductor (CMOS) image sensors, cooled and uncooled focal plane arrays, active pixel sensors, and more It has important application prospects. However, in high-density application scenarios, due to the mismatch in thermal expansion coefficients between the silicon substrate and the TSV interconnection metal, TSVs have serious thermal stress problems, which will cause transistor mobility and parameter shifts to affect device performance and even cause device damage. , it is urgent to suppress the impact of thermal stress on device reliability through structural regulation.
Jiao Binbin's team innovatively proposed a "football-like" TSV structure that is narrow at both ends and wide in the middle, closed at both ends and hollow in the middle. It has the characteristics of small aperture, high aspect ratio, and low stress. The inwardly collapsing stress-buffering hollow structure provides stress relief space for TSV, which can significantly reduce the stress and electromigration of the substrate silicon. It can withstand large temperature difference operating conditions. The sealing structure at both ends is compatible with the subsequent traditional spin coating process. , has universal applicability. At present, the TSV structure with the largest depth (>100μm), the largest aspect ratio (>20.3:1), and the smallest residual stress (31.02MPa) reported internationally has been achieved. Its diameter is 5μm, the center distance is 25μm, and the number of TSVs reaches 320,000. (Density 1600/mm 2 ), effective connectivity rate reaches 100%, and is the only TSV solution that can withstand extremely low temperature conditions (-200°C).
