Guangli Microelectronics creates 3D IC yield solutions to support the development of the Tao Law ecosystem.
In the post-Moore era, the semiconductor industry is embracing a new paradigm centered on Tao's Law, a time-scale theory that enables performance breakthroughs in HPC, AI computing, and automotive chips. This approach leverages advanced technologies such as:
Logic Folding (reducing transistor counts per module),
Ultra-narrow pitch hybrid bonding (<1.5μm),
TSV multi-stack architectures,
And sub-0.5μm alignment precision.
However, these advancements introduce significant yield and process challenges:
Extreme hybrid bonding requirements: CMP (chemical-mechanical polishing) flatness control and <0.5μm overlay accuracy are critical; even ppm-level open defects can cause batch failures.
Wafer-to-wafer parameter mismatch: Logic folding often combines wafers from different batches/nodes, amplifying timing variability and reducing timing margins.
Testing bottlenecks for massive 3D chips: 64/96-core stacked dies face overcrowded DFT (Design-for-Test) routing, high test data volumes, expensive equipment needs, and incomplete fault coverage especially for automotive safety standards like ISO
To address these hurdles, Guangli Microengineering has developed an independently researched technology matrix spanning the entire chip lifecycle:
1. DFM Simulation & Hybrid Bonding Control (TQV)
2. Advanced Process Control (Adv-PCM)
3. 3D-Specific DFT Testing (QuanTest)
A comprehensive solution tailored for stacked chips:
SDS High-Speed Scan Bus: Each core features a local scan host, reducing top-tier DFT routing by 90% and cutting test time by 4x; ideal for HBM, large-scale heterogeneous SoCs, and 3D stacks.
On-Chip Compare IP: Minimizes ATE (Automatic Test Equipment) pin requirements while supporting "Partial Good Die" yield scenarios with built-in failure diagnosis.
ATPG + SAFA Fault Injection Fusion: Closes cross-asynchronous domain testing gaps to achieve >99% fault coverage compliant with ISO 26262, critical for automotive and AI chips.
As Moore's Law slows, Tao's Law is driving the next generation of semiconductor integration. Guangli Microengineering's integrated "DFM simulation + high-density electrical testing IP + fast test equipment + AI-based yield platform + 3D DFT" stack addresses critical bottlenecks in:
Chip design (via DFM tools),
Manufacturing (process monitoring & bonding control),
Testing (3D-specific DFT and high-speed WAT), and
Packaging (hybrid bonding validation).
By providing domestic alternatives to foreign tools, Guangli Microengineering strengthens China's ability to scale 3D IC production for AI accelerators, HPC systems, and automotive electronics. This collaboration with industry partners underscores a broader ecosystem shift toward native Chinese innovation in advanced semiconductor architectures.