Chinese semiconductor thread II

[tokenanalyst]

VeriSilicon launches CPP2000 camera post-processing IP, empowering embodied robots and mobile vision applications.​

The CPP2000 integrates multiple image processing technologies to further optimize YUV images output from image signal processors. This IP supports image and video processing at resolutions up to 8K and offers various hardware configuration options to meet the design requirements of different applications in terms of power consumption, performance, area (PPA), and latency. Through the synergistic effect of multiple image processing technologies, including motion-compensated temporal filtering, advanced spatial noise reduction, chroma adjustment and dynamic contrast enhancement, and edge enhancement, the CPP2000 achieves comprehensive optimization of image noise, sharpness, contrast, and detail, thereby improving image stability and visual performance in mobile imaging scenarios and providing high-quality image input for subsequent visual perception and machine vision applications.

“Providing high-quality images for robots and drones requires a holistic imaging solution that goes beyond image signal processors and encompasses advanced camera post-processing technologies. High-quality images are not only the foundation for achieving high-fidelity visual effects, but also the key to enabling reliable AI perception, navigation, and decision-making. As next-generation robots become increasingly reliant on image perception, the demand for high-quality images continues to grow, making comprehensive image enhancement increasingly important for achieving robust visual performance,” said Weijin Dai, Chief Strategy Officer, Executive Vice President, and General Manager of the IP Business Unit at VeriSilicon. “The CPP2000 addresses these challenges through advanced camera post-processing technologies, significantly improving image quality in complex mobile camera application scenarios. Combined with VeriSilicon’s comprehensive vision processing IP portfolio, the CPP2000 will help customers develop more robust, intelligent, and energy-efficient vision systems to meet the needs of next-generation robots, drones, and other mobile vision applications.”

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[tokenanalyst]

Huifeng Diamonds: Another CVD diamond project goes into production!​

Huifeng Diamonds officially commenced production at its Baotou CVD diamond industrialization project in Kundulun District. This milestone coincides with the 105th anniversary of the Communist Party of China and marks a significant step for the company's "Second-Stage Entrepreneurship."

The completion of this project fulfills a key component of Huifeng's national production capacity layout. It solidifies the company's role as a comprehensive service provider for high-end functional diamond materials, establishing a domestic mass-production foundation for superhard materials with independent control.

Synthetic diamonds are now recognized as national strategic materials under the "15th Five-Year Plan." They have moved beyond traditional industrial uses to include critical roles in semiconductors, AI computing power, aerospace, and 6G communications. Due to their high value and security implications, synthesis equipment is listed on export control lists.

As AI chip power consumption rises, traditional materials (copper/aluminum) have hit limits. Diamond's superior thermal conductivity makes it the optimal solution for computing heat dissipation, opening a "trillion-dollar" market opportunity.​

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[tokenanalyst]

Xinge Microelectronics Secures Orders for Domestic Board-Level Lithography Equipment​

Xinge Microelectronics has secured a significant order from a key customer in the advanced packaging sector. The equipment involved is the PLP 2000. The PLP 2000 represents China's first board-level packaging direct-write lithography equipment with a processing area of 510×515mm (capable of up to 600×600mm). This marks the company's successful transition from wafer-level applications to larger, panel-level manufacturing. This breakthrough addresses a critical gap in China's semiconductor supply chain by providing independent capabilities for advanced packaging, which is essential for high-performance chips driven by AI, 5G, and HPC needs.

The PLP 2000 is engineered to meet the rigorous demands of evolving packaging technologies:​

• Resolution: Achieves a mass production resolution of 2μm, satisfying requirements for complex processes like CoPoS (Chip on Panel on Substrate), glass substrates, and FOPLP.​
• Scale & Efficiency: Designed for large-format exposure to ensure higher production efficiency and scalability compared to traditional wafer-level methods.​
• Precision & Consistency: Features systematic design elements ensuring micron-level pattern resolution, high-precision alignment, and uniformity across entire boards—critical factors for yield and interconnect reliability.​

The deployment of this equipment reduces reliance on foreign technology, promoting a more complete and controllable domestic manufacturing ecosystem for advanced packaging. Xinge Microelectronics aims to expand its product matrix further into high-density interconnects and new substrate materials, continuing its mission "Lithography Changing the World" to support China's semiconductor industry upgrade.

The winning of this order validates Xinge Microelectronics' industrialization capabilities and positions it as a leader in next-generation large-format lithography equipment, directly supporting the shift toward heterogeneous integration and high-density interconnects required by modern computing architectures.

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[tokenanalyst]

FWave: a fast 3D resist model with dual-branch architecture for EUV lithography simulation​

​

Abstract​

Rigorous physical resist models are highly accurate but computationally expensive. Specifically, solving reaction-diffusion equations to predict inhibitor concentration severely limits simulation speed. Furthermore, compared to deep ultraviolet (DUV), extreme ultraviolet (EUV) lithography introduces stochastic effects, resulting in irregular pattern edges. To overcome these challenges, we propose FWave, a fast 3D resist model for inhibitor concentration prediction during PEB. FWave utilizes the dual-branch architecture: the Fourier neural operator (FNO) branch efficiently captures global features, while the discrete wavelet transform (DWT) branch extracts edge variations caused by EUV stochastic effects. Additionally, a spatially weighted mean squared error (WMSE) loss function is employed to accurately fit contact hole regions. Applied to EUV contact hole simulations, FWave demonstrates sub-nanometer critical dimension (CD) errors and achieves a approximately 2000x speedup compared to rigorous physical model.

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[tphuang]

Xinge Microelectronics Secures Orders for Domestic Board-Level Lithography Equipment​

Xinge Microelectronics has secured a significant order from a key customer in the advanced packaging sector. The equipment involved is the PLP 2000. The PLP 2000 represents China's first board-level packaging direct-write lithography equipment with a processing area of 510×515mm (capable of up to 600×600mm). This marks the company's successful transition from wafer-level applications to larger, panel-level manufacturing. This breakthrough addresses a critical gap in China's semiconductor supply chain by providing independent capabilities for advanced packaging, which is essential for high-performance chips driven by AI, 5G, and HPC needs.

The PLP 2000 is engineered to meet the rigorous demands of evolving packaging technologies:​

• Resolution: Achieves a mass production resolution of 2μm, satisfying requirements for complex processes like CoPoS (Chip on Panel on Substrate), glass substrates, and FOPLP.​
• Scale & Efficiency: Designed for large-format exposure to ensure higher production efficiency and scalability compared to traditional wafer-level methods.​
• Precision & Consistency: Features systematic design elements ensuring micron-level pattern resolution, high-precision alignment, and uniformity across entire boards—critical factors for yield and interconnect reliability.​

View attachment 177584

The deployment of this equipment reduces reliance on foreign technology, promoting a more complete and controllable domestic manufacturing ecosystem for advanced packaging. Xinge Microelectronics aims to expand its product matrix further into high-density interconnects and new substrate materials, continuing its mission "Lithography Changing the World" to support China's semiconductor industry upgrade.

The winning of this order validates Xinge Microelectronics' industrialization capabilities and positions it as a leader in next-generation large-format lithography equipment, directly supporting the shift toward heterogeneous integration and high-density interconnects required by modern computing architectures.

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when you post stuff like this, can you post the Chinese link please in the future?

here is what I can find

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芯碁微装/CFMEE has developed PLP-2000 Panel-level packaging direct-write lithography system, first by a Chinese company. 510x515mm large panel for high-end IC substrates & ultra-large panel advanced packaging with applications in HBM & AI compute chip packaging substrate. This gives domestic OSAT & substrate makers a local alternative for PLP. Resolution claim is down to 2μm line/space for advanced packaging RDL, bumping, TSV applications. This is different than the stepper lithography by AMIES. It is more for CoWoS-L & FOPLP types of panels.

 

[tokenanalyst]

You are correct, looks like I forgot to put the link. I only put the link of the company.

Resolution claim is down to 2μm line/space for advanced packaging RDL, bumping, TSV applications. This is different than the stepper lithography by AMIES. It is more for CoWoS-L & FOPLP types of panels.

PLP-2000 is a maskless digital lithography machine. The latest stepper lithography machine from AMIES is a projection lithography machine with a resolution down to 350 nm and can be use to make ICs, power chips, RF and so on.

AMIES do have packaging machines with a large field of view and I think different from AMIES, the PLP-2000 require stitching, I think that is why the resolution is constrained to 2um.

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[tphuang]

https://twitter.com/i/web/status/2073151815902797885

Pango Micro with Titan-3 series FPGA that is 100m+ class number of gates using FinFet process and supports DDR4.