Chinese semiconductor thread II

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Dinglong Technology! Breakthrough in CMP Polishing Fluid​


Recently, Hubei Dinglong Holding Co., Ltd. (hereinafter referred to as "Dinglong") issued an announcement regarding significant progress in its CMP polishing slurry products. Dinglong's subsidiary , Wuhan Dingze New Material Technology Co., Ltd. (hereinafter referred to as "Dingze New Material"), has recently made continuous breakthroughs in the field of semiconductor CMP polishing slurries.
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( 1) Core products won the Outstanding Supplier Award from leading wafer foundry customers;

Recently, Dingze New Materials received the "Excellent Supplier" award from a leading domestic logic chip foundry , recognizing its outstanding performance in the stable supply and supporting services of high-kJ metal gate (HKMG) and copper process CMP polishing slurry. HKMG alumina polishing slurry is a core material for advanced process chip manufacturing, an industry long monopolized by overseas companies. This type of product faces high verification barriers and is difficult to replace on client production lines, exhibiting extremely high technical barriers and stringent process compatibility requirements.

( 2) The copper barrier polishing slurry received a new customer's bulk order;

Dinglong Technology's independently developed mature process copper barrier layer polishing slurry, relying on its excellent process adaptability, stable product quality, and outstanding overall cost advantages, has successfully passed the rigorous, high-standard verification of a domestic mature process wafer fab, and recently won a bulk purchase order from this customer. This order marks Dinglong Technology's third copper process polishing slurry product order from a customer, signifying that the versatility and adaptability of Dinglong Technology's copper barrier layer polishing slurry products have been widely verified and recognized by the industry, successfully achieving market implementation for multiple customers and in multiple scenarios, and further enriching and improving Dinglong Technology's full range of copper process CMP polishing slurries.

( 3) Silicon carbide (SiC) substrate polishing slurry has successfully secured a batch of orders, and the core raw material of the polishing slurry—self-abrasive material—has officially entered the third-generation semiconductor market.

Dinglong Technology 's SiC substrate polishing slurry, developed and produced using its independently controllable alumina abrasive , has successfully secured bulk purchase orders from domestic customers. This marks the official entry of the company's self-developed and self-produced abrasive system polishing slurry into the field of third-generation semiconductor SiC substrate polishing, achieving a key breakthrough for the company in the third-generation semiconductor materials market from 0 to 1, and is of great milestone significance.

Among the polishing slurries mentioned above, polishing slurries containing alumina abrasive particles and copper process polishing slurries (including copper and copper barrier layer polishing slurries) are key consumables in wafer manufacturing and are also the mainstream categories in the domestic polishing slurry market. It is estimated that these two types of products will account for over 20% and 45% of the polishing slurry market value, respectively, with the combined domestic market size expected to exceed 4 billion yuan by 2026. Silicon carbide polishing slurries belong to the emerging consumables field of third-generation semiconductors, an industry still in its early stages of growth with vast market development potential.

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Impact of active area and gate line width roughness on SRAM stability: role of low-frequency noise and process variability in advanced IC manufacturing​

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Abstract​

As complementary metal oxide semiconductor (CMOS) technology scales, static random-access memory (SRAM) stability is increasingly jeopardized by process variability. While the impact of gate line width roughness (LWR) on spatial variability has been widely documented, the distinct role of active area (AA) LWR—particularly its correlation with temporal low-frequency noise (LFN)—remains poorly understood. This study bridges this gap by presenting a systematic experimental investigation using a production 55nm CMOS hard-mask (HM) process to decouple the effects of AA and gate LWR. Contrary to conventional wisdom that focuses solely on dimensional uniformity, we discover a novel physical mechanism: reducing AA LWR mitigates boundary scattering at the shallow trench isolation, which directly suppresses the intrinsic LFN of the device by approximately 1 dB. This suppression of temporal noise is critical for low-voltage operation. Furthermore, we establish a dual-regime yield theory: experimental data prove that low-voltage yield is predominantly limited by LFN, whereas nominal-voltage yield is governed by spatial variability (device mismatch). Quantitative analysis reveals that a 1 nm reduction in AA LWR decreases temporal read static noise margin (RSNM) fluctuation by 37.6%, resulting in a 13.1% increase in normalized low-voltage yield. In contrast, gate LWR reduction primarily enhances spatial matching, improving parametric yield by 10.2% at nominal voltage. These findings provide a physics-guided co-optimization strategy for advanced patterning processes, offering specific design rules to manage spatiotemporal fluctuations beyond simple process tweaks.

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Shanghai Lixin, a pioneer in domestic digital EDA end-to-end solutions, showcased its expertise at the 2026 Chipchip Conference.​


At this year's Semiconductor Show, Shanghai Lixin Software Technology Co., Ltd. (hereinafter referred to as "Lixin"), as a local supplier dedicated to developing collaborative intelligent EDA tools for integrated circuit design and manufacturing, made a grand appearance with four core products: LeDI Digital Realization Platform, LePI Power Integrity Platform, LePV Physical Verification Platform, and Le3DIC Design Platform.

Founded in 2020, Lixin aims to create reliable tools for chip design and manufacturing, and help build an independent and controllable chip design and manufacturing ecosystem. Its core products cover key areas such as digital realization process, physical verification and approval, 3DIC/Chiplet system-level design and DTCO.

The LeDI digital implementation platform focuses on the entire chip digital design process, covering the complete implementation chain from RTL to GDSII, providing chip design companies with a one-stop digital implementation toolchain that is independent, controllable, and high-performance. The platform includes design tools such as process design co-optimization (LeDTCO), logic and physical synthesis optimization (LeSyn), automatic layout planning optimization (LePlan), automatic placement and routing optimization (LeAPR), parasitic parameter model extraction (LeRCG), simulation-level timing analysis engine (LeSTA), and domestic advanced process DRC special repair (LeDRF). Its full-process co-optimization tool (LeCompiler) provides users with a complete digital implementation toolchain that is compatible with mature and advanced process nodes.
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LePI is a signature-based toolset for power integrity and reliability analysis of mixed-signal chips . It supports on-chip power consumption, resistance, voltage drop, and electromigration analysis, as well as the generation of chip power consumption models. It also supports full-chip power signature analysis with various package models. LePI solutions cover EMIR analysis for both 2D and 3D ICs from early design to signature stages. Validated by high-volume customer designs, its accuracy, performance, and capacity for EMIR analysis in both mature and advanced processes rival industry benchmark tools.
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LePV is a physical verification and approval tool covering four major modules: DRC, LVS, DFM, and PERC, all of which have been verified through high-volume customer designs. The overall product matrix covers these four key verification stages, ensuring both accuracy and efficiency, and is suitable for full-chip physical verification workflows using advanced processes.
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Le3DIC is an integrated design platform for 3DIC and advanced packaging , providing a complete solution from 3D heterogeneous integration planning and collaborative placement and routing to simulation analysis. Based on a hierarchical data foundation, the platform supports early design planning and system-level interconnect optimization across multiple processes and stacking architectures. It features heterogeneous chip collaborative placement and routing capabilities and 3D system timing analysis, enabling overall optimization of system-level timing, power consumption, and area. It establishes a consistent closed loop from early planning to approval verification, significantly reducing design iterations, improving efficiency and accuracy, and helping customers achieve systematic development and approval-level reliable verification of 3D stacked designs.
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Acousto-optic Q-switched 745 nm alexandrite laser for 248 nm DUV source generation​

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Abstract​

A 745 nm laser with high peak power and narrow linewidth is a crucial source for the generation of a 248 nm deep ultraviolet (DUV) laser. Here, an acousto-optic (AO) Q-switched narrow linewidth 745 nm alexandrite laser is reported, which is pumped by a 638 nm laser diode (LD). Based on a dual-end pumped L-shaped cavity, the continuous-wave (CW) laser achieved a maximum output power of 3.34 W. Q-switched operation at 1–10 kHz repetition rates was also realized via an acousto-optic modulator (AOM), generating an average power of 2.66 W at 10 kHz. In addition, at a 1 kHz repetition rate, the laser can deliver a single pulse energy of 524 µJ, with a pulse duration of 238.4 ns and a peak power of 2.2 kW. A 1-mm-thick birefringent filter (BRF) was inserted into the cavity for linewidth narrowing and enabled wavelength tunability across 728–773 nm. The maximum single pulse energy of 330 µJ was also obtained at a 5 kHz repetition rate, which is the highest pulse energy as far as we know for an LD-pumped AO Q-switched narrow-linewidth alexandrite laser. At the central wavelength of 745 nm, the system delivered a single pulse energy of 250 µJ and a pulse duration of 346.7 ns at 4 kHz with a spectral linewidth of 0.44 nm. The beam quality factors M x 2 and M y 2 were measured as 1.25 and 1.11, respectively. By introducing two BBO crystals inside the cavity, it was confirmed that a 248 nm DUV source was generated based on the intracavity cascaded second-harmonic generation (SHG) and third-harmonic generation (THG) scheme.

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