Chinese semiconductor thread II
- Thread starter vincent
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So that big jump from 2030 to 2031 isn't necessarily due to EUV? The increases in density seem to plateau a little after around 2028 but then suddenly increase again so I'm wondering what could cause such a big increase from out of nowhere.
a huge density & clock speed jump happens between 2030 & 2031 likely to related with EUV and you can't suddenly introduced EUV it means they will have working EUV machine before 2030.
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what i have noticed Huawei pushing hybrid bonding to the extreme. this is mind boggling. i just simplified it for the general audience.
Huawei wrote their own scaling law. they just presented the Tau (τ) Scaling Law at IEEE ISCAS, a framework that replaces geometric transistor scaling with time-based optimization across devices, circuits, chips, and systems.
To address the high thermal density issues brought by advanced processes + 3D stacking, a type of ultra-thin, quiet, and more efficient chip-level active cooling technology has been developed, which is part of a system-level solution.
After Huawei's Hi-ONE (near-package optics) and 3D Folding, the thermal density of chip packaging will rise significantly, and traditional cooling methods are no longer sufficient. Therefore, this chip-level active cooling solution is being developed in parallel, and the supporting technologies are quite interesting.
One more interesting thing Huawei announced ''2026 will be a big density jump in transistors''
Edit - honestly there is so much to discuss. hopefully one by one i could post or maybe @tphuang sir. but an exciting time ahead.
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Could be EUV. Could be adding another layer of “folding”. Could be both. If they feel comfortable with the folding approach taking over as the primary performance driver they may simply stop chasing an aggressive node shrink schedule and EUV adoption may start more with improving the nodes Huawei has already reached rather than pushing their shrinking cadence. But of course one can only speculate for now.
Why are they saying their 2025 Chip Transistor density is 155 MTr/mm2? As far as I remember, Kirin 9030Pro has a transistor density of around 125MTr/mm2. 155 MTr/mm2 places it well beyond TSMC N5 which I don't think is true based on performance of the chip. Note Huawei Chips are more optimized for performance in Core level compared to Snapdragon
I wonder how this plays out with Huawei's Ascend roadmap from last year.
We saw a big jump in performance after around 2028, similar to what we've seen for the Kirin map.
Either way I think we can expect a pretty major breakthroughs in the years to come, from EUV or folding.
It could refer to a chip that's never been seen in the open market. For example the ARM v9 SoCs with onboard HBM, that's being used in the Lingsheng exascale supercomputer, that we discussed few weeks ago, is believed to be a new Huawei Kunpeng chip. In December 2024 Huawei submitted a patch to the Linux kernel for a new Kungpeng chip with onboard HBM.
They are using theoretical density from the fab, actual performance will vary because you can't make every single part at exactly the highest density possible. 9050 data is probably also theoretical, actual average density will likely be quite a bit lower.
Two posts
I think both can be true at the same time.
I think both can be true at the same time.
Huawei likes to show off but only when they can put their money where their mouth is. I suspect Hank is trying to do some confidence management against Huawei fans since there are a lot of folks in Chinese industry who don’t like Huawei’s aggressive tactics and eventually policymakers will have to curtail some of Huawei’s broader ambitions.