paper
A Time Scaling Theory for Multi-Layer Electronic Systems
I was wrong. She didn't mention EUV. Big increase due to more folding.note the big increase in year 2030. I think this is the timeline for EUV.
No one "mentions" EUV in China.I was wrong. She didn't mention EUV. Big increase due to more folding.
Confirms what I surmised. Seems like they just broke open the whole chip design space. One paradigm shift in concept that just unlocked 10 parading shifts in design.
In this case they seem to have just done it without a major leap in the process node size. What they’re announcing here isn’t 3D “stacking” in the sense of sandwiching two chips together vertically, but an actual full 3D native design layout organized around time efficiency of logical operations as the optimization principle. With this approach they were able to get major per area transistor density gains as well as clock speed gains while also scoring significant energy efficiency gains. What this also means is that when they get to EUV they won’t need to match node shrinks to match performance with the frontier. At equivalent node sizes we could be talking 2x transistor density/performance or even 3-4x if they get more ambitious with the number of transistor layers they “fold” in. That said it may also be the case that doing aggressive node shrinks for this “LogicFold” approach may be more challenging and have slower cadence since I can see some of the fabrication details being harder to do.No one "mentions" EUV in China.
Similar to Huawei's own roadmap for Ascend. Really impressive specs for chips in the 2027 to 2028 period.
Almost impossible to be able to squeeze that out with DUV reasonably at scale. Which is why it points to advancements in lithography.
Design 101: Go vertical and shortest path.In this case they seem to have just done it without a major leap in process mode. What they’re announcing here isn’t 3D “stacking” in the sense of sandwiching two chips together vertically, but an actual full 3D native design layout organized around time efficiency of logical operations as the optimization principle. With this approach they were able to get major per area transistor density gains as well as clock speed gains while also scoring significant energy efficiency gains. What this also means is that when they get to EUV they won’t need to match node shrinks to match performance with the frontier. At equivalent node sizes we could be talking 2x transistor density/performance or even 3-4x if they get more ambitious with the number of transistor layers they “fold” in. That said it may also be the case that doing aggressive node shrinks for this “LogicFold” approach may be more challenging and have slower cadence since I can see some of the fabrication details being harder to do.
Whatever improves operation speed under a power constraint, which in the most immediately addressable sense is often dictated by shortest distance traveled for your electrons for each unit of logic switches and each interconnect point between units, or alternatively points of resistance along the electrical path for logical operations that cause time delay and power drain as dictated by path length or other factors, but in theory not exclusively just that.Design 101: Go vertical and shortest path.