Wafer-level packaging integration of LPDDR5X-signal integrity design and simulation exploration.
China Electronics Technology Group Corporation 58th Research InstituteIn the past 10 years, excessive research enthusiasm has been focused on 2.5D/3D advanced packaging (e.g. CoWoS/SoIC) used for data-center artificial intelligence (AI) chips and high bandwidth memory integration. For the edge AI chips with lightweight computing power, very thin FBGA (VFBGA), low power double data rate 5/5X (LPDDR5/5X) and wafer-level (WL) packaging with the redistribution layer (RDL)-first process are the integration technology trends. This paper focuses on AI system on chip (SoC) and LPDDR5X on-package integration design only using 3 RDL on the WL package. This paper aims to examine the influence to explore the trace routing scheme and corresponding signal integrity (SI) performance of the RDL interconnection for the on-package LPDDR5X, thereby providing RDL design and simulation reference for the ever-increasing demand for AI SoC and LPDDR5X on-package integration that is an alternative for on-board interconnection.

