300mm silicon wafers are the cost-benefit sweet spot, especially for advanced nodes. By comparison, wafer cost estimates for 450mm are nowhere near commercially viable. I don't know the latest cost estimates, but a few years ago it was something like 5 times more than 300mm. The main reason was related to problematic crystal growth at the margins of 450mm silicon ingots with resultant yield issues. With such an excessive wafer cost, any potential savings per die from processing a 450mm wafer does not offset the extra cost, let alone be more cost effective than 300mm.
Yep!
That's not correct. In the past, semiconductor makers like IBM and Intel pushed for the for conversion to 200mm and 300mm. For the 450mm push, it was Applied Materials. The problem is that Applied supplied nearly all the different types of equipment to make a chip, but forgot the most important part - they didn't have a lithography technology. Yes they had bought Etec for direct write ebeam, but that wouldn't work for chip production. So they contacted ASML. Problem is ASML told them they were developing their EUV system and didn't have the resources to develop DUV systems for 450mm at the same time EUV systems for 300mm. Subsequently, the infrastructure is in place that the possibility of 450mm equipment keeps getting pushed out, again primarily because of heavy burden EUV is placing on ASML to expand capacity to make more that 40 a year. Remember their newer system is 3 years delayed.
Actually, it is correct. What you said doesn't detract from what was the main problem, which is that growing silicon ingots towards 450mm encountered intractable problems with edge defects that largely nullified the wafer size advantages with yield issues. For example, you can grow an artificial diamond to say a few carats size, but it becomes increasingly difficult to scale that up to say 10000 carats, assuming that was the goal.
Thank you. Each transition to a larger wafer results in edge exclusion issues. Initial 450mm wafers development at Albany had 3mm edge exclusions, but that was reduced to 2mm and G450C consortium was pushing for 1.5mm plus the possibility of removing the notch. At the time immersion was the only viable litho technology and Nikon and ASML were the only ones making them. Nikon never moved to EUV and as you know ASML is over their head with developing EUV systems with better k and higher throughput, and their efforts back in 2013 on 450mm was just the beginning of their need to spend large sums of money and engineering time to get the technology off the ground. The Japanese wafer manufacturers just experienced a wafer plant damaging earthquake impacting money for 450mm development at a time when there was also a downturn in the semi industry. And they refused to spend more money on 450mm platforms when they were working on improved immersion DUV and EUV on 300mm platforms. So the edge exclusion was an issue, but there are many more that were involved.
yes folks 50%. This kind of monopolistic pricing is unsustainable as other FABS like SMIC increase construction of matured processes to avail themselves of possible dissatisfied customers. What angered me is that they had the gall and audacity to call others of looming glut in the market while they increase prices...LOL. By bundled together the price increase of all processes, they are planning to pass the cost of 3nm development knowingly that even Apple their VIP customer will not accept such price increases. Why not make hay while the sun shine and make perfect excuse of the current Chip shortage...LOL
TSMC Price increase again in all processes due to continuous drop of their gross profit from previous 2 quarters to 50%
Perfect timing for the Chinese IC equipment and FAB makers, an inclusive growth is possible up to 14nm and even 7nm, the market is there any investment will have a quick ROI with the current Chip shortage. It had become a growth sector with plenty of money to be made.