From the the 25th China Integrated Circuit Manufacturing Annual Conference
Wang Mengya, a senior technical expert of the 58th Research Institute of China Electronics Technology Group Corporation, gave a speech titled "Microsystem Reliability Design Based on Chip Integration Technology".
Chiplet, in fact, decomposes complex functions, and then develops a microchip with a single function that can be assembled modularly to build a microchip physical library. According to a jigsaw puzzle, the above-mentioned various microchips are mixed and integrated into an interposer, which is often called a silicon brick board to achieve some functions. Academician Xu, an authoritative domestic authority, defines chips as commercialized. Unpackaged bare chips with specific IP are packaged together through advanced integration technology like building blocks, mainly for the multiplexing of hard IP.
Through the above advanced definition, the development of chips mainly relies on two key technologies, one is advanced packaging technology to achieve physical interconnection between chips. It is possible to use IC processes such as common process, conventional process, and low-power process, and use the middle process of front-end and back-end integration to achieve a performance improvement. In fact, the design is more flexible, the cost is lower, and the cycle is shorter.
The other is the standard technology of the interface , which realizes the electrical interconnection between chips. In 2022, Intel, together with dozens of manufacturers such as AMD, released an open industry standard UcIe, which provides a high-bandwidth, low-latency, low-power, and low-cost packaging interconnection for Chiplets from different sources.
The reliability of microsystems based on chip integrated systems is also a difficult design difficulty. The reliability of the microsystem is analyzed from the aspects of design, process and detection.
In terms of design, it is necessary to carry out simulation tests of multiple physical scenarios such as electricity, heat, and force, and tests for signal integrity and power integrity.
In terms of technology, there are mainly wafer reconfiguration, wafer-level rewiring, wafer-level bump preparation, and three-dimensional stacking, etc., mainly focusing on several key technologies such as TSV, chip to wafer, RDL, and bump.
In terms of detection, the existing IEEE1838 standard mainly solves the interoperability and testability of the three-dimensional stacking of chips. It must be aimed at the particularity of microsystems. Based on the current integrated circuit test platform, it is necessary to praise a chip-based, micro-component , The multi-level test platform of the microsystem, and form the corresponding test methods and test specifications to ensure the reliability of the microsystem in all aspects.
The 58 Institute has a platform for the entire industrial chain in the field of integrated circuits, including a 7-nanometer design platform, a 65-nanometer mask platform, a national ceramic packaging center, a microsystem center line, etc., and has rich experience in the microsystem field. It has successively established 8-inch and 12-inch mid-way lines, and released the PDK of wafer-level fan-out packaging. A service platform for testing reliability, including 3D X-ray testing, scanning acoustic microscopy testing, etc.