Chinese semiconductor industry

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tokenanalyst

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I didn’t find any mention of the interferometers in the critical improvements introduced to NXT:2050i. Maybe they were already good enough?
1-For the development of this new immersion scanner, ASML collaborated with various teams and suppliers on the wafer handler (VDL), the wafer stage (VDL and Kyocera), the wafer table (Berliner Glass), the production of the immersion hood (AAE), the reticle stage (ASML’s Wilton factory) and the projection lens (Zeiss). Cymer and Gigaphoton from Japan delivered a pulse stretcher on the lasers that reduced the speckle, resulting in much lower scanner-induced line-width roughness.

2-The reticle isn’t exposed in a flash of light, like in a stepper, but in a scanning way, just like a photocopier. For this, the scanner has to hold the reticle stage, move the reticle and clamp and hold the wafer on the wafer table. “Not only to flatten it but also to keep it at the right temperature and hold and move the wafer,” explains Paarhuis. The forces released by these movements are impressive and have to be counterbalanced. However, minor overlay errors caused by these accelerations can still be seen as a nanopattern in the exposures: the errors vary from row to row and from field to field. The 2050 system offers increased stiffness and integrated damping in the wafer stage. Paarhuis: “We were able to reduce the overlay errors by more than a factor of two.”

3-To decrease the overlay errors and simultaneously improve productivity, ASML had to do substantially more wafer alignment measurements in less time. “On the NXT:2000 system, we could measure 28 alignment marks at 275 wafers per hour,” says Paarhuis. “Without extra measures to accelerate the measurements, we ended up locating only 20 alignment marks at 295 wafers per hour.” To do all checks in time, the 2050 team accelerated the alignment scans and measurements of the wafer height map. “We made them faster and were also able to optimize the routing in between the marks.”
As a result, the 2050 system can measure 55 marks at 295 wafers per hour. “This enables a better overlay because we can more accurately measure the shape of the wafer.”


4-A few years ago, ASML found another overlay error contribution. Paarhuis: “Analyzing the data, we discovered a very typical scan-up-scan-down fingerprint.” This distortion pattern is caused by the DUV pellicle and contributes to the errors in DUV-EUV matching.
The solution is running a model on the scanner that reduces the pellicle impact. “Using the reticle stage trajectory, we can predict the pellicle bending and use a model to calculate the needed overlay corrections and apply them during exposures.” This works pretty well, says Paarhuis. The model predicts the required correction with an error of only 0.1-0.2 nanometers. “That’s very nice.”

I think 3 and 4 are algorithmic optimizations but those optimizations require better sensors with very low overhead to really make a impact in performance.
They did changed in 2017 their SMASH alignment sensor with a new improved ORION alignment sensor, so i guess that require better improved interferometers.

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PopularScience

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I know Bloomberg, among many others, is not reliable and has a strong anti-china agenda. Indeed I wrote "if confirmed".

Regarding the big order of SMIC to ASML at the end of last year, I remember I read here in the forum a couple of weeks ago, but now I am not able to find the source.

Regarding delivery SMEEE DUV 28nm machine, we discussed at length around havoc words. For instance this is a data point, there are more:


According to havoc, DUV immersion machine, currently at SMIC's, will be delivered to customer "soon" for testing but not for mass production. From delivery to mass production usually 12-18 months occurs. Also this has been discussed at length.
 

paiemon

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Bro my 2 cents, we know that SMEE will officially announce the debut of SSA800 DUVL this year, from the technical spec we know it matches that of NXT 1980i, So why would the Chinese buy an equivalent machine with uncertainty due to geopolitics? only NXT 2050i and NXT 2100i will do because that is what needed and that opportunity window will close in 2025 with an improved SSA900 22NM variant or even an EUVL. I think there is a realization in Netherlands and ASML in particular that they have 5-6 years to profit from China BUT the timeline will fasten to 2 years if they stupid enough to follow the American advise.
We won't know until we see details of the rollout, but given that SMEE's capacity will be limited initially, if ASML machines are available Chinese fabs will certainly buy them to meet their goals despite any reservations. Of course to your point over the long run that will be in doubt if the reliability of ASML supplies is put into question and SMEE or other Chinese institutes come up with competitive offerings. Given how long it has taken the Dutch government to get to this point, I am sure they are pondering/weighing all those scenarios as you described.
 

tokenanalyst

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Unprecedented investment in silicon wafer enterprises and accelerated production capacity construction

In recent years, the state has established an integrated circuit industry fund, the capital market has launched a science and technology innovation board, local and social capital have actively participated, the integrated circuit industry has smooth financing channels, and the financing difficulties of semiconductor silicon wafer enterprises have been effectively resolved. Shanghai Silicon Industry Group Co., Ltd., Zhejiang Leon Microelectronics Co., Ltd., and Youyan Semiconductor Silicon Materials Co., Ltd. entered the capital market to raise funds to develop the semiconductor silicon wafer industry. Xi'an Eastwell Wafer Technology Co., Ltd. and Hangzhou Zhongxin Wafer Semiconductor Co., Ltd. have obtained social capital support, and at the same time actively strive for listing on the Science and Technology Innovation Board. With the strong support of capital, domestic backbone semiconductor wafer enterprises have developed rapidly, forming a fairly good industrial foundation, and significantly enhancing the support and guarantee capabilities for the domestic semiconductor industry.

Shanghai Silicon Industry Group Co., Ltd. has achieved mass supply of 12 in silicon wafers, and plans to increase the production capacity of 3×10^5 wafers on the basis of the current monthly production capacity of 3×10 5 wafers, and at the same time add 3.12×10^6 wafers per year 8in semiconductor polishing wafer production capacity. Based on the production capacity of 1.7×10^5 pieces/month for 12-in silicon wafers and 7.5×10^5 pieces/month for 8-in silicon wafers, TCL Zhonghuan New Energy Technology Co., Ltd. plans to build 6×10^5 12-in silicon wafers by the end of 2023 pieces/month, 8 in silicon wafers 1×10^6 pieces/month capacity. Based on the monthly production capacity of 5×10^5 wafers for 12-in silicon wafers, Xi’an Eastwell Silicon Wafer Technology Co., Ltd. plans to increase the production capacity of 5×10^5 wafers/month from 2022 to 2026. Zhejiang Leon Microelectronics Co., Ltd. has established a production capacity of 2.7×10^5 8-in polished wafers per month and 1.5×10^5 12-in silicon wafers per month. It is under construction with an annual production capacity of 1.8× 10^6 12-in silicon wafers, Annual production of 1.2×10^6 pieces of 8 in silicon wafer project. Hangzhou Zhongxin Wafer Semiconductor Co., Ltd. has built a production capacity of 4×10^6 pieces/month of 8 in silicon wafers, with an annual output of 1.2×10^6 under construction 8 in, annual output of 2.4×10^5 pieces of 12 in epitaxial wafer project. Youyan Semiconductor Silicon Materials Co., Ltd. has completed the construction of large-scale silicon wafer industrial base for integrated circuits, supplied 8-in silicon wafers in batches, and its large-scale production line of 3×10^5 pieces /month 12-in silicon wafers is under construction.

At present, domestic 8-in silicon wafer technology can meet domestic demand, is in the stage of capacity release, and the localization rate continues to increase; 12-in silicon wafers have entered the market in batches, the technical level has gradually improved, and the industrial supporting capacity has been significantly enhanced.
 

CMP

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Samsung has chip industry vacancies for Taiwanese to fill because China has been pillaging their (Samsung's) work force. Taiwan is blocking Taiwanese from going to China for chip work, so instead they'll go to South Korea while the South Koreans go to China. Flow of capital and labor, especially highly educated/skilled and scarce to boot, has a way of working itself out despite government obstruction. Especially when that government is a weak provincial one with almost no real influence or power.
 

Weaasel

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If confirmed this is a bad news. The clear target here is ASML....and SMIC.

ASML is going to ban the most advanced DUV immersion machines at the same node level of the banned US equipment, i.e for nodes below 20/16nm.

This is not a random thought, but is the official position of ASML CEO and, we can assume, of the Dutch government during the negotiations with US.

So to workaround this, US will move up the technological threshold of banned US equipment to include the whole DUV immersion range, i.e. up to 28nm included....and of course, the day after they put into effect this new rule, they will knock at the Dutch government's door.

For US toolmakers is not a big loss, because they are out anyhow or will be soon. Moreover the localization efforts of Chinese firms have already almost closed the gap at 28nm for a large part of US equipment.

For ASML instead this would be a heavy blow. The biggest impact I see is on the big order of ASML machines that SMIC (supposedly) made in November last year with delivery in 2024. IMO US is aiming at stopping that.

For China it means to wait until the end of 2024 for 28nm in volume production and more or less another 1/2 years for 14nm/16nm.
If it will really be such a blow for ASML, then the Netherlands should be brave enough to defy the United States...
 

Weaasel

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You're thinking too much in terms of commercial applications and market share. The main reason the US wants to deny China advanced chip making capabilities isn't because of a petty fight over trade profits. It's because advanced chips enable strategic capabilities that the US would very much like to monopolize - specifically 4th Industrial Revolution technologies like AI, IoT, robotics, AR, 5G/6G, as well as related military applications. It's the national security establishment making the calls, not the commerce department. If it were commerce focused, the US wouldn't be encouraging China to make its own chips, it'd do what it's done for the past four decades, which is to frustrate every Chinese effort at indigenizing chip production by making it easy for Chinese companies to just buy what it wanted.

That strategy worked so incredibly well at ensuring that no Chinese competitor ever emerged in chip production, that there's no reason at all why the US would switch from it, but for the fact that the national security people couldn't tolerate China having access to high-end chips any more.
That strategy worked so incredibly well in part because the Chinese State was less resolved back then on ensuring that there is a comprehensive indigenous supply chain from refining of silicon, to making IC chips, and various semiconductors and IC chips manufacturing equipment, granted though now the full realization that the Americans plan on potentially banning EVERYTHING has brought even the most liberal traders in China in line with regards to comprehensive indigenization.
 

tphuang

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YMTCPhase2.jpg
So this on xueqiu. YMTC phase 2 IIRC. The fab itself was already built. Not sure, why it says here that the work will start this month.

Does that mans they are finally moving equipment in? I thought that was ongoing already?

Also, says monthly designed production is 6350PB. What does that translate to in terms of wpm?

Anyway, the total Capex is 109.9B RMB, so a lot of money. huge investment
 
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