Chinese semiconductor industry

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tokenanalyst

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In Europe practically all companies, not only listed ones, should prepare an annual financial statement and send to competent authorities that makes it available upon request to the public. Usually you pay a small fee to access financial statement of a specific company. Is quite common to do this to check some customer, supplier, etc.
SMEE is a subsidiary of a bigger company called the Shanghai Electric Group, so is up to the that company to make the financial reports. Makes me wonder if SMEE would be in better in the hands of Beijing E-Town, they already have RSLaser, CNEPO and CHEERTECH, why not have SMEE and UPrecision in the hands of a group that better understand the Chinese semiconductor industry than Shanghai Electric or Tsinghua.
 

latenlazy

Brigadier
In Europe practically all companies, not only listed ones, should prepare an annual financial statement and send to competent authorities that makes it available upon request to the public. Usually you pay a small fee to access financial statement of a specific company. Is quite common to do this to check some customer, supplier, etc.
Doesn’t work like that in China.
 

antiterror13

Brigadier
In Europe practically all companies, not only listed ones, should prepare an annual financial statement and send to competent authorities that makes it available upon request to the public. Usually you pay a small fee to access financial statement of a specific company. Is quite common to do this to check some customer, supplier, etc.

yes, also in NZ to IRD (Tax authority) to declare basically the profit/loss, I think the same for everybody in the world, including China. But I don't think the P/L statement is for public, thats a confidential information unless the court decided to open it. Well, that in NZ anyway.

I wouldn't want my P/L and my Tax return is open to public :rolleyes:
 

sunnymaxi

Captain
Registered Member
To my understanding what the guy hpvc is saying that if you go the public available information (from 10 years ago) you find that it use a underpower 20W ArF DUV laser when ASML use a 60W Arf laser, has an 0.75NA lens system limiting the resolution when ASML can reach 0.9NA, is single stage with a disappointing MMO and low acceleration when ASML stage are dual (can do metrology), precise and fast. All of that translate to very disappointing WPH. My personal opinion hpvc is extrapolating that information to today to make an assessment.
I say that a lot has change from 10 years ago, U-Precision wafer stages are more precise, faster and dual stage. Rslaser subsystems are much more powerful. China CAS and Guowang Optical have develop better lenses and lens systems, they have better and more precise fabrication tools and so on.
They have reached the same level of ASML? I don't know, but they are in a much much better position than 10 years ago IMHO.
no one can deny it. even a staunch critics of China will agree with your statement.

difference in between 2010 China and today's China is like heaven and earth.
 

sunnymaxi

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China's RF front-end chip companies are rising rapidly, with an established competition pattern in the smartphone market. And they still need to work hard on technologies for filters, high-density packaging, and high-performance power amplifiers. These are the key points of a report on China’s RF frond-end chip sector by JW Insights analyst Zhao Yi. More summaries from the report.

The global smartphone market is sluggish in 2022, and the Chinese smartphone market is worse with a prolonged replacement cycle and insufficient purchasing power. In the next 2-3 years, China's smartphone sales may remain at 270-280 million units annually.
The China-produced front-end chips are used widely in both low-end and flagship Chinese smartphones. The global market share of China's RF front-end chip companies has reached more than 10%. If Apple, Samsung, and other manufacturers are excluded, the localization rate of RF front-end devices in China has reached more than 25%.

The Chinese companies have occupied a large market in Phase2/Phase5N PA and discrete switch low-noise amplifiers. They are catching up in fields like LPAMiF/PAMiF and DiFEM/LFEM, and they still lag behind in LPAMiD /PAMiD and high-performance filters like TC-SAW and IHP-SAW.

With the continuous improvement of China’s PA module companies and technology breakthroughs in filter companies, it will be a trend for PA and filter companies to integrate in the future. It is expected that Chinese PAMiD will be gradually introduced in 2022, with a certain scale of shipments in 2023.
 

tinrobert

Junior Member
Registered Member
Assumptions you referenced from @tinrobert is incorrect. 10DUV is not enough for 50K wpm of 28nm. No scanners or steppers available today is that fast. I will spare you the details since you are not going to believe me anyway.

But, you can go research:
- how many litho steps it take to make a 28nm wafer
- how fast a scanner/stepper can expose a wafer
- when ASML/Nikon/Canon/SMEE say for example 220 wph, the 'wafer' here means single exposure of a wafer
- by the way, this is the theoretical maximum throughput based on ideal conditions.

To be close to reality, you'll also need to consider (estimate) the scanner availability (uptime, utilization rate), wafer yield, wafer rework rate, etc.

Once you have all this info you could determine number of scanners required and conclude if my/@tinrobert's estimate is correct.

28/45/55nm are all planar process. The total litho steps to build a chip is quite similar. The main differences is distribution of each layers of the chip between scanners of varying capabilities (iLine, KrF, ArF, ArFi).

Some variation do exist between the chip design and process. 28nm typically have a few more metal/via layers, so 45nm node would roughly be 44-46 litho steps. The difference are in the number of iLine layers and saving of $10M.

Besides, I'm sure SMIC already determine the intended product mix to come up with the $7 to 8B announced CAPEx. For reference, a true 100% 28nm fab like the on UMC is building in Singapore costs $3.6B for 30K wpm or $12B for 100K wpm.

I don't think SMIC ever took delivery of SSA600. SMIC did take delivery of a SSB600 a few years ago, but that tool was never qualified for HVM. I inferred from information from others in the industry that Yangdong may have took on the challenge to help SMEE qualify a 200mm SSA600/20.

I think you misunderstood what SSA600's true capability is. But that's okay, I have not seen anyone share anything of substance beyond the info ("claims") that's published on SMEE's website.

It's widely known in the industry SMEE reverse engineer the SSA600/10 off of ASML's old scanner. SSA600 is based on very old technology that was introduced in the late 1990s for 200mm wafers production. Looking at its 0.75NA lens, it was reverse engineered from ASML PAS5500/1150C. SMEE published many papers on SSA600/10 & SSA600/20 this past decade. Hardware, software, and specifications given in those papers are consistent with the 'reverse engineered' narrative.

The SSA600 was never qualified in the field by any fabs. But if it was verified to have met all its specifications, it would have:
- resolution limit of 90nm
- throughput of >130wph @ 200mm
- 300mm wafer has more area to cover than 200mm
- at tool acceptance condition, 300mm is based on 96 & 200mm on 46 exposure fields (in reality, fields/wafer number is generally higher so actual throughput on product will be lower)
- so if SSA600 is used on 300mm wafers the ideal tool acceptance test throughput specification would be closer to >65wph
- this (very low throughput) is why only a 20W 4KHz laser is required & used

In contrast, a modern day Nikon/ASML ArF scanners all have 0.93 NA with resolution limit around 65nm with throughput in excess of 230wph (300mm wafers).

Even the modern day Nikon/ASML/Canon KrF scanners have higher NA that ranges between 0.80 to 0.93 with resolution limit of 80nm and throughput up to 330wph.

With the old ArF technology, SSA600/20, even if it works properly, what would be its place in the fab. An ArF scanner that underperforms a KrF scanner with much larger Cost-per-wafer would have a hard time finding a niche in a HVM fab.

All specifications in this last subject matter/section could be compiled off public info online. I verified each of them while typing this up.
It takes 10 DUV immersion scanners to process 45K wpm at 28nm node, 16 at 22nm, 19 at 10nm. It takes 15 DUVi at 7nm plus 6 EUV. I don't know where tphuang got my quote, and I may have been referring to SMIC reaching 7nm without EUV and substituted DUV for EUV. You're statement that my 10 DUVi demand at 28nm is not correct is wrong. It is correct.
 

ansy1968

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Registered Member
The Japanese follow suit cutting production behind the South Korean and Micron might slow down its 232 layer production as YMTC increase theirs. In this downturn the underdog might gain some BIG customer (Apple) from the established players.

A good summary of the conundrum they're facing and a golden opportunity for YMTC to seized upon. ;)

Given such drastic 3D NAND price reductions, it is not surprising that Kioxia is cutting down its output to reduce its inventory levels. It is unclear how other 3D NAND makers will react, but in the end, they have two options: keep production of flash memory at the current levels and grab market share from Kioxia by offering lower prices and potentially lose money, or reduce the output to keep supply and demand in balance to at least fix prices at current levels.

From TOM's Hardware.

Kioxia Slashes 3D NAND Production as SSD Sales Plummet​

By
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published 1 day ago
Kioxia is among the first to acknowledge the adjustment of 3D NAND output.

Kioxia

(Image credit: Kioxia)

Kioxia said it would cut down production of 3D NAND memory at its fabs located at its Yokkaichi and Kitakami sites. Demand for PCs and many other devices is slowing due to high inflation rates, geopolitical tensions, and macroeconomic factors, producers of commodities like 3D NAND want to reduce inventories and avoid oversupply, so they have to cut down production.

Kioxia said it would reduce its wafer starts by approximately 30%, starting from tomorrow. However, a 30% reduction of wafer starts does not automatically mean a 30% reduction of 3D NAND bit output, as depending on the exact process technologies used to process wafers, the effect on bit output can be quite different. In addition, Kioxia did not say how long it plans to cut its 3D NAND wafer production.
Kioxia operates its fabs and shares its output with Western Digital, and while the American company has not issued any similar statements as of the time of writing, we would expect it to follow suit.

Kioxia is not the first to slash 3D NAND output, yet it is the first company to put the cards on the table and make a more or less detailed announcement. Micron said on Thursday that it was ‘reducing utilization in select areas in both DRAM and NAND,’ which essentially means a production cut. Meanwhile, there is no word (again) about NAND bit output, but only about the utilization of fabs, which reduces bit output per se. Perhaps nobody outside of Micron knows exactly what output was cut, so it is not our business to make such assumptions.
Also, Micron said it would slow down the production ramp of its latest 232-layer 3D NAND memory devices to reduce costs associated with the ramp and avoid oversupply on the market, which will inevitably affect the prices of flash memory and storage devices like solid state drives (SSDs), including the best SSDs aimed at enthusiasts.”

In fact, earlier this week, analysts from
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that the price of 3D TLC NAND and 3D QLC NAND wafers dropped by 30% ~ 35% in the third quarter compared to the second quarter and would decline by another 20% ~ 25% in Q4 compared to Q3 because of slowing demand for new PCs, servers, and consumer electronics.
Given such drastic 3D NAND price reductions, it is not surprising that Kioxia is cutting down its output to reduce its inventory levels. It is unclear how other 3D NAND makers will react, but in the end, they have two options: keep production of flash memory at the current levels and grab market share from Kioxia by offering lower prices and potentially lose money, or reduce the output to keep supply and demand in balance to at least fix prices at current levels.
 

tphuang

Lieutenant General
Staff member
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It takes 10 DUV immersion scanners to process 45K wpm at 28nm node, 16 at 22nm, 19 at 10nm. It takes 15 DUVi at 7nm plus 6 EUV. I don't know where tphuang got my quote, and I may have been referring to SMIC reaching 7nm without EUV and substituted DUV for EUV. You're statement that my 10 DUVi demand at 28nm is not correct is wrong. It is correct.
IIRC, I took it from your article about SMIC reaching 7nm without EUV.

Assumptions you referenced from @tinrobert is incorrect. 10DUV is not enough for 50K wpm of 28nm. No scanners or steppers available today is that fast. I will spare you the details since you are not going to believe me anyway.

But, you can go research:
- how many litho steps it take to make a 28nm wafer
- how fast a scanner/stepper can expose a wafer
- when ASML/Nikon/Canon/SMEE say for example 220 wph, the 'wafer' here means single exposure of a wafer
- by the way, this is the theoretical maximum throughput based on ideal conditions.

To be close to reality, you'll also need to consider (estimate) the scanner availability (uptime, utilization rate), wafer yield, wafer rework rate, etc.

Once you have all this info you could determine number of scanners required and conclude if my/@tinrobert's estimate is correct.

28/45/55nm are all planar process. The total litho steps to build a chip is quite similar. The main differences is distribution of each layers of the chip between scanners of varying capabilities (iLine, KrF, ArF, ArFi).

Some variation do exist between the chip design and process. 28nm typically have a few more metal/via layers, so 45nm node would roughly be 44-46 litho steps. The difference are in the number of iLine layers and saving of $10M.

Besides, I'm sure SMIC already determine the intended product mix to come up with the $7 to 8B announced CAPEx. For reference, a true 100% 28nm fab like the on UMC is building in Singapore costs $3.6B for 30K wpm or $12B for 100K wpm.
Actually, I make no determination whether your statement or tinrobert's statement was correct. Since I don't work in this industry, I consider both to be plausible. It seemed like your estimation for the # of required DUVi for 28nm was about twice as his. That's fine, I can consider one as an upper bound and the other as lower bound.

I had a problem with you making an assertion of how quickly SMIC can scale up based on immersion scanners they were buying and Capex them were scanning. it's quite clear based on their stated Capex and how many immersion scanners they could purchase. Based on my calculation, they are allocation about $5.5 to 6 billion for equipment purchases at both Beijing and Tianjin and a little more at the Shanghai Lingang plant. As such, there is no indication they are just building 28 nm wafers or even 45/55 nm wafers. I think they are building a wide range of mature node wafer due to the tremendous industrial demand in China.

And again, they are not the only one footing the bills here. The local government are sharing the Capex in order to attract fabs on their property. I guarantee you that SMIC will be spending less Capex on its new fabs and lower annual operating cost than any other chip makers in the world.

That's how they are able to announce 340k wpm of 12-inch wafers in 3 years and possibly even more than that. They are looking at adding about 15 to 20% 8-inch equivalent wafer capacity per year. A large chunk of that will not be 28 nm and lower or even 45/55 nm.

I don't think SMIC ever took delivery of SSA600. SMIC did take delivery of a SSB600 a few years ago, but that tool was never qualified for HVM. I inferred from information from others in the industry that Yangdong may have took on the challenge to help SMEE qualify a 200mm SSA600/20.

I think you misunderstood what SSA600's true capability is. But that's okay, I have not seen anyone share anything of substance beyond the info ("claims") that's published on SMEE's website.

It's widely known in the industry SMEE reverse engineer the SSA600/10 off of ASML's old scanner. SSA600 is based on very old technology that was introduced in the late 1990s for 200mm wafers production. Looking at its 0.75NA lens, it was reverse engineered from ASML PAS5500/1150C. SMEE published many papers on SSA600/10 & SSA600/20 this past decade. Hardware, software, and specifications given in those papers are consistent with the 'reverse engineered' narrative.

The SSA600 was never qualified in the field by any fabs. But if it was verified to have met all its specifications, it would have:
- resolution limit of 90nm
- throughput of >130wph @ 200mm
- 300mm wafer has more area to cover than 200mm
- at tool acceptance condition, 300mm is based on 96 & 200mm on 46 exposure fields (in reality, fields/wafer number is generally higher so actual throughput on product will be lower)
- so if SSA600 is used on 300mm wafers the ideal tool acceptance test throughput specification would be closer to >65wph
- this (very low throughput) is why only a 20W 4KHz laser is required & used

In contrast, a modern day Nikon/ASML ArF scanners all have 0.93 NA with resolution limit around 65nm with throughput in excess of 230wph (300mm wafers).

Even the modern day Nikon/ASML/Canon KrF scanners have higher NA that ranges between 0.80 to 0.93 with resolution limit of 80nm and throughput up to 330wph.

With the old ArF technology, SSA600/20, even if it works properly, what would be its place in the fab. An ArF scanner that underperforms a KrF scanner with much larger Cost-per-wafer would have a hard time finding a niche in a HVM fab.

All specifications in this last subject matter/section could be compiled off public info online. I verified each of them while typing this up.
hmm, reports like this one
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says that 1 SSA600 was delivered to SMIC Shaoxing and to YMTC back in end of 2020 and early 2021 (according to that article, these are just the bid that it won during that time. So does not include non-bid sales).

And this looks to be from a sales pitch SMEE made in March
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Notice how it says it has 30% of local market for the front end lithography in there and lists SMIC, YMTC, HLMC, Huahong Grace and GTA as customers?

On top of that, 90 nm lithography machine was recently announced by Shanghai government as being under mass production at the same time 14 nm production was announced. We know that by now, SMIC has been producing 14 nm for several years, so Shanghai gov't likely only announced process/machines that are already in mass production.

That's all I know. I'm not speculating on how good SSA600 is. I'm also not speculating at this moment when SSA800 will be delivered for use with customers. I am say that you cannot measure the expansion pace of these new SMIC fabs based just on SMIC's own Capex and DUVi deliveries from ASML. SMIC has basically given us a pretty solid guidelines of when these fabs are going into production. I think we should just go by those numbers.

Again, I think they've already purchased enough DUVi for SN1 and a good chunk of Chinese DUVi purchase this year are for SMIC SN2 plant. Which leads me to think SN2 will start production in 2023. How fast it fully ramps up to 35k wpm is depend on if there is any interruptions to ASML deliveries and any other equipment producers. I would put 2025 as a likely time horizon for them to reach 70k wpm between SN1 and SN2.
 

ansy1968

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Registered Member
YMTC is one of the companies which might be affected by US export bans on tools.
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But bro did they De Americanized their whole production system? and I think its rather late in the game, they should done it earlier and I think with the downturn China is the only bright spot and ASML may disagree with SMEE upping their game with near peer equipment.
 
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