Tsinghua EUV photoresist patent was approved.
Chinese semiconductor thread II
- Thread starter vincent
- Start date
China's first "gallium nitride driver chip" for robot joints is officially commercialized
Recently, China Science Wireless Semiconductor Co., Ltd. announced that its robot joint ASIC driver chip based on gallium nitride (GaN) HEMT process has been officially launched and commercialized. It is specially designed for actuators and motor drives on the joints of embodied robots, industrial robots, and medical robots. It is a member of the "Robot Joint Driver Chip Series" in China Science Semiconductor's robot power system chip family.
The mass production this time includes three cost-effective models for different application scenarios (CT-1906 fully integrated, CT-1904 topology design, CT-1902 single integrated). The driving capability covers "high power density scenarios of frameless torque motors, RV reducers, harmonic reducers, planetary reducers, cycloid reducers, planetary roller screws, bearing assemblies, servo motors, hydraulic actuators and pneumatic actuators". The chip shows broad application prospects. It marks another important breakthrough of Zhongke Semiconductor in the field of robot ASIC power system chip technology.
The official commercial model released this time is CT-1906. The LGA package integrates 6 GaN HEMTs (three-phase half-bridge topology) and 3 independent drivers, supporting 80V continuous voltage/100V transient voltage, 60A continuous current output and 5MHz switching frequency. At the same time, Zhongke Semiconductor also launched the CT-1904 and CT-1902 series. Through unified device specifications (GaN FET performance, packaging process) and hierarchical integration strategies, it reduces the customer's multi-platform development costs, achieves seamless connection from "full integration" to "scalability", and meets the differentiated needs of industrial automation, new energy equipment and embodied intelligence. Technical advantages The chip has high integration, high reliability, low power consumption and comprehensive protection mechanisms.
looks like they have data-centers level HDL simulation to dozen of billions logic gates, no transistors, gates.
A new height of domestic capacity, Hejiangongsoft releases data center-level full-scenario hardware simulation platform UVHP.
Shanghai UniVista Hyperscale Emulator ( UVHP ), a data center-level, full-scenario, ultra-large-capacity hardware simulation acceleration and verification platform, is announced by Shanghai UniVista Industrial Software Group Co., Ltd. ("UniVista Hyperscale Emulator ") , which is the first domestically developed hardware emulator that can be expanded to 46 billion logic gates. It also supports further expansion of multiple systems, which can greatly improve the simulation and verification efficiency and shorten the simulation and verification cycle of ultra-large-scale chips.
The ultra-large capacity hardware simulation acceleration platform UVHP is based on the new generation of proprietary hardware simulation architecture independently developed by Hejiangongsoft. It adopts advanced commercial FPGA chips, the original high-performance RTL synthesis tool UVSyn , intelligent fully automatic compiler, and rich high-speed and low-speed interface and storage model solutions to provide strong support for the simulation verification of ultra-large-scale ASIC/SOC .
Application areas such as AI intelligent computing, HPC supercomputing, AD/ADAS intelligent driving, 5G , and ultra-large-scale networks are driving the scale, functional integration, and software and hardware system-level complexity of chip design to increase significantly. This places higher demands on the capabilities of verification tools and brings challenges to verification in diverse scenarios. In addition to providing faster and more accurate compilation and more efficient debugging capabilities for chip design and development, verification tools must also have a more flexible and unified full-scenario verification platform. This can not only improve fault correction efficiency and verification throughput, but also reduce the risk of large-scale complex chip tape-outs, and provide powerful digital twin capabilities for software and hardware collaborative simulation verification .
UVHP, the hardware simulation acceleration verification platform newly launched by Hejian Software, has achieved a new height of energy efficiency and capacity for domestically developed hardware simulation acceleration platforms. The platform has increased the computing power of the hardware simulation system to the data center level, and the system scale supports 160 million gates to 46 billion gates. It is the first domestically developed hardware simulator that can be expanded to 46 billion logic gates, and its performance is comparable to that of international advanced products. The full-scenario verification mode includes a variety of solutions such as pure hardware environment, XTOR and Hybrid, providing powerful computing power support for chip system-level hardware and software collaborative design and verification.
A new height of domestic capacity, Hejiangongsoft releases data center-level full-scenario hardware simulation platform UVHP.
Shanghai UniVista Hyperscale Emulator ( UVHP ), a data center-level, full-scenario, ultra-large-capacity hardware simulation acceleration and verification platform, is announced by Shanghai UniVista Industrial Software Group Co., Ltd. ("UniVista Hyperscale Emulator ") , which is the first domestically developed hardware emulator that can be expanded to 46 billion logic gates. It also supports further expansion of multiple systems, which can greatly improve the simulation and verification efficiency and shorten the simulation and verification cycle of ultra-large-scale chips.
The ultra-large capacity hardware simulation acceleration platform UVHP is based on the new generation of proprietary hardware simulation architecture independently developed by Hejiangongsoft. It adopts advanced commercial FPGA chips, the original high-performance RTL synthesis tool UVSyn , intelligent fully automatic compiler, and rich high-speed and low-speed interface and storage model solutions to provide strong support for the simulation verification of ultra-large-scale ASIC/SOC .
Application areas such as AI intelligent computing, HPC supercomputing, AD/ADAS intelligent driving, 5G , and ultra-large-scale networks are driving the scale, functional integration, and software and hardware system-level complexity of chip design to increase significantly. This places higher demands on the capabilities of verification tools and brings challenges to verification in diverse scenarios. In addition to providing faster and more accurate compilation and more efficient debugging capabilities for chip design and development, verification tools must also have a more flexible and unified full-scenario verification platform. This can not only improve fault correction efficiency and verification throughput, but also reduce the risk of large-scale complex chip tape-outs, and provide powerful digital twin capabilities for software and hardware collaborative simulation verification .
UVHP, the hardware simulation acceleration verification platform newly launched by Hejian Software, has achieved a new height of energy efficiency and capacity for domestically developed hardware simulation acceleration platforms. The platform has increased the computing power of the hardware simulation system to the data center level, and the system scale supports 160 million gates to 46 billion gates. It is the first domestically developed hardware simulator that can be expanded to 46 billion logic gates, and its performance is comparable to that of international advanced products. The full-scenario verification mode includes a variety of solutions such as pure hardware environment, XTOR and Hybrid, providing powerful computing power support for chip system-level hardware and software collaborative design and verification.
They are also working with Loongson in PCB design software.
Recently, the high-end large-scale PCB design platform UniVista Archer independently developed by Shanghai Hejian Industrial Software Group Co., Ltd. (hereinafter referred to as "Hejian Gongsoft"), a leading domestic digital EDA company, has been successfully adapted to the Loongson 3A5000/3A6000 Dragon architecture desktop terminal, becoming the first EDA product in China to complete adaptation and operation on the Dragon architecture terminal, and realizing the closed loop of the domestic electronic system design platform from electronic hardware design tools to hardware R&D platforms. This breakthrough not only marks a key step for domestic EDA tools in the field of self-controllability, providing a solid foundation for the self-controllability of the "China Core" ecosystem, but also verifies the excellent performance and wide applicability of Loongson 3A5000/3A6000, laying a solid foundation for the in-depth cooperation between Loongson Zhongke and Hejian Gongsoft in the future.
In this adaptation, Loongson Technology and Hejian Software worked closely together to overcome challenges in technical compatibility and performance optimization, ensuring the stable operation and efficient performance of UniVista Archer on the Loongson architecture platform. Users can easily develop domestic chip projects through the domestic UniVista Archer EDA software on the Loongson desktop terminal.
New breakthrough in collaboration! Loongson terminals and Archer software of Hejiangongsoft are successfully adapted
Recently, the high-end large-scale PCB design platform UniVista Archer independently developed by Shanghai Hejian Industrial Software Group Co., Ltd. (hereinafter referred to as "Hejian Gongsoft"), a leading domestic digital EDA company, has been successfully adapted to the Loongson 3A5000/3A6000 Dragon architecture desktop terminal, becoming the first EDA product in China to complete adaptation and operation on the Dragon architecture terminal, and realizing the closed loop of the domestic electronic system design platform from electronic hardware design tools to hardware R&D platforms. This breakthrough not only marks a key step for domestic EDA tools in the field of self-controllability, providing a solid foundation for the self-controllability of the "China Core" ecosystem, but also verifies the excellent performance and wide applicability of Loongson 3A5000/3A6000, laying a solid foundation for the in-depth cooperation between Loongson Zhongke and Hejian Gongsoft in the future.
In this adaptation, Loongson Technology and Hejian Software worked closely together to overcome challenges in technical compatibility and performance optimization, ensuring the stable operation and efficient performance of UniVista Archer on the Loongson architecture platform. Users can easily develop domestic chip projects through the domestic UniVista Archer EDA software on the Loongson desktop terminal.
Zhongwei Optoelectronics releases economical OHT overhead crane system, making intelligent logistics within reach.
Recently, Hangzhou Zhongwei Optoelectronics Technology Co., Ltd. (hereinafter referred to as "Zhongwei Optoelectronics"), a subsidiary of Jingsheng Electromechanical Group, officially released its fully self-developed economical OHT (Overhead Hoist Transport) crane system, which provides economical and efficient aerial logistics solutions for the semiconductor, panel, packaging and testing industries and other multi-point logistics scenarios.
The system adopts a fully enclosed track design and builds an aerial logistics network that meets the requirements of a clean environment, which can significantly improve the utilization rate of plant space. By integrating intelligent algorithms and digital twin technology, the system achieves precise trajectory planning and real-time monitoring, with a positioning accuracy of ±2mm and a transport speed of up to 2m/s, supporting 7×24 hours of uninterrupted operation.
Based on years of automation experience, Zhongwei Optoelectronics has created a cost-effective domestic solution. Compared with other OHT systems, the OHT system released by Zhongwei Optoelectronics this time has a larger load capacity, stronger customization capabilities, a wider range of applicable scenarios, and a variety of track support forms, which can be quickly spliced and adjusted, and the transformation and expansion are more flexible. In addition, the system's full stack of software and hardware is self-developed, the entire system is domestically produced, and modularly designed, with a short delivery cycle and low deployment cost. The overall cost is only 25% of that of a high-end magnetic levitation OHT system. These technological breakthroughs and advantage control reflect Zhongwei Optoelectronics' ability to differentiate its OHT system and allow more companies to enjoy the efficiency improvements brought by smart logistics.
The system adopts a fully enclosed track design and builds an aerial logistics network that meets the requirements of a clean environment, which can significantly improve the utilization rate of plant space. By integrating intelligent algorithms and digital twin technology, the system achieves precise trajectory planning and real-time monitoring, with a positioning accuracy of ±2mm and a transport speed of up to 2m/s, supporting 7×24 hours of uninterrupted operation.
Based on years of automation experience, Zhongwei Optoelectronics has created a cost-effective domestic solution. Compared with other OHT systems, the OHT system released by Zhongwei Optoelectronics this time has a larger load capacity, stronger customization capabilities, a wider range of applicable scenarios, and a variety of track support forms, which can be quickly spliced and adjusted, and the transformation and expansion are more flexible. In addition, the system's full stack of software and hardware is self-developed, the entire system is domestically produced, and modularly designed, with a short delivery cycle and low deployment cost. The overall cost is only 25% of that of a high-end magnetic levitation OHT system. These technological breakthroughs and advantage control reflect Zhongwei Optoelectronics' ability to differentiate its OHT system and allow more companies to enjoy the efficiency improvements brought by smart logistics.
Jiazhicai OLED De-mura equipment officially shipped to a leading domestic panel manufacturer
Recently, the official WeChat public account of Kailun Holdings announced that the first domestic OLED De-mura equipment used in the 8.6-generation line independently developed and manufactured by Suzhou Jiazhicai Optoelectronics Technology Co., Ltd. (hereinafter referred to as "Jiazhicai"), a subsidiary of the company, has been officially shipped to a leading domestic panel manufacturer. This move marks a substantial breakthrough in the core link of OLED manufacturing for domestic high-end display testing equipment, which has significantly improved the independent guarantee capability of my country's new display industry chain.
It is reported that De-mura (i.e. Mura defect repair) is a key process in OLED panel production. It uses a high-precision optical inspection system to identify uneven brightness and color of the panel, and uses a precise compensation algorithm to repair it, greatly improving display uniformity and picture quality.
Previously, the technical barriers for high-performance OLED De-mura equipment suitable for large-generation lines (especially 8.6-generation lines) were high, and the market has long been dominated by overseas manufacturers. As a high-tech enterprise focusing on core process equipment for high-end display panel production, Jiazhicai has successfully overcome core technologies such as high-speed and high-precision detection of ultra-large-size, high-resolution OLED panels, automatic classification of complex Mura defects, and generation and writing of ultra-precision compensation data based on its deep technical accumulation. The 8.6-generation line OLED De-mura equipment delivered this time was fully independently designed and developed by Jiazhicai and has intellectual property rights. The main technical indicators have reached the domestic advanced level.
alright, first quarter revenue ranking for DRAM and 3D Nand
this is fantastic stuff. It seems like before this year, they just weren't even tracking CXMT and YMTC revenues. But now, these two are expanding very quickly. Especially as they move up to more layers NAND and DDR5 DRAM
this is fantastic stuff. It seems like before this year, they just weren't even tracking CXMT and YMTC revenues. But now, these two are expanding very quickly. Especially as they move up to more layers NAND and DDR5 DRAM
Interesting development.. Let's see how many Chinese chip design companies are going to start using them instead of waiting for Nvidia to come up with another new downgraded product for China. Lol
Yeah exactly, but that happened already.
Steve Hsu, someone who kind of knows the ins and outs of the industry.
Says he was in Shanghai, having dinner with the number #2 guy at SMIC.
Then he said, in fact, everyone sitting at the table for dinner, including himself, all from Taiwan one way or another.
Assassinsmace posted the video in that other thread.
Start at 28:18 for that.
That is the people-ware.
As for the hardware, that really is a state secret, but the rumours make it sound imminent.
My layman guess is EUV machine ready by this year, then next year EUV chip production, or the year after at the latest.