Chinese semiconductor industry

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tokenanalyst

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Like i say before Huawei is going to give China what the Chinese government
tokenanalyst said:
There are major issues with 3D stacking that need to be resolved mostly about thermal issues, but there is no incentive for unsanctioned companies to solve it because they could just keep adding transistors to a single die until they hit the limit, while Huawei is under great pressure to innovate to survive sanctions. So Huawei investing in 3D stacking makes sense, but not so much for other companies.
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I said before, Huawei is likely to give China what the Chinese government failed in decades, a bottom-up semiconductor industry. These penalties could backfire spectacularly.
 
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antonius123

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ansy1968 said:
@antonius123 bro TW, SK and the US all had EUVL, why would they choose another processes when they had the tool available? Stifling China will only spur it to innovate more and 3D stacking is one of them.
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Simple reason: because 3D stacking could improve the performance of chip and they are competing for the highest chip performance.
Why don't they go with 3nm + 3D stacking if it could outcompete their competitor?
 
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ansy1968

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FairAndUnbiased

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ansy1968 said:
@antonius123 bro I'm not an expert, but from what I learned 3D stacking is doable in DUVL and other processes but not in EUVL, I hope @tokenanalyst @krautmeister @WTAN @FairAndUnbiased can help me out.
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no its doable in 3 nm. The question is how many 3 nm chips can you afford to stack when each wafer is worth 16k vs. 9k for a 7 nm wafer (even down to just 1k for older wafers), and with the understanding that as die shrinks occur the more and more transistors are useless due to thermal constraints?

a 3 nm wafer that's 80% useless dark silicon costs 16k, but you could have a 7 nm wafer for the core for 9k with 28 nm peripherals and that's maybe 12k total, but none of the peripherals are dark silicon and maybe only 50% of the 7 nm wafer is dark silicon.

and there's design complexity to consider. Do you actually need 3 nm? Remember everything is money. You can have a toilet made of solid diamond and gold like Trump, is it cost effective though? Does it do the job?
 
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tokenanalyst

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antonius123 said:
Simple reason: because 3D stacking could improve the performance of chip and they are competing for the highest chip performance.
Why don't they go with 3nm + 3D stacking if it could outcompete their competitor?
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Makes not economic sense when you have free access to cutting edge fabs and 3nm alone already offer enough performance over the last generation, 3d stacking at 3nm size will add interconect complexity way beyond 14nm or 7nm, this are not 2D dies in substrate anymore, this are stacks. For Huawei makes sense to invest in 3d stacking because is already stuck at 14nm and i think stacking mature nodes is not as complex as stacking GAAFET ICs.
 
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antonius123

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tokenanalyst said:
Makes not economic sense when you have free access to cutting edge fabs and 3nm alone already offer enough performance over the last generation, 3d stacking at 3nm size will add interconect complexity way beyond 14nm or 7nm, this are not 2D dies in substrate anymore, this are stacks. For Huawei makes sense to invest in 3d stacking because is already stuck at 14nm and i think stacking mature nodes is not as complex as stacking GAAFET ICs.
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So they need to calculate which more economical is between: 3nm + 3D stacking vs 2nm/1nm for the similar performance. If the 3D stacking with 3nm is still cheaper then there is incentive to pursue it.

Basically the feasibility of 3D stacking technically and economically could be always compared to the next generation/smaller node.
 
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krautmeister

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ansy1968 said:
@antonius123 bro I'm not an expert, but from what I learned 3D stacking is doable in DUVL and other processes but not in EUVL, I hope @tokenanalyst @krautmeister @WTAN @FairAndUnbiased can help me out.
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It's doable whether as a fully EUV direct wafer bonding process or as a combination of EUV and DUV packaging. I'm not even sure they could have get 3D stacking working reliably in EUV at <=3nm. There's already so many issues with electron bleeding that yields might just make this a non-starter. Besides, the main issue is it's overly complex for relatively small gain vs big increase in cost. China is hitting the wall at 7nm until it has its own EUV. There is no choice and no other options. For everybody else, the cheaper, easier path is simply maxing out the EUV processes until they hit the silicon limit. Then they will be in the same boat as China is with their own wall. It's the same logic as why 450mm wafers aren't pursued seriously even though it is technically possible and could and would have superseded 300mm. The price performance curve doesn't warrant it.
 
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